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USGreg
 

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  1. USGreg
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    <p><a href="https://stackexchange.com/users/2220163/greg"><img src="https://stackexchange.com/users/flair/2220163.png" width="208" height="58" alt="profile for Greg on Stack Exchange, a network of free, community-driven Q&amp;A sites" title="profile for Greg on Stack Exchange, a network of free, community-driven Q&amp;A sites" /></a></p> <p>Staff Verification Engineer with over 10 years of professional experience, plus RTL implementation and schematic experience. When I'm not resolving bugs, I'm finding ways maximize quality of the design, streamline verification, and teaching other best practices. Other skills on my tool belt: C, C++, Perl, GNUmakefile.</p> <p>I am a advocate of <a href="/questions/tagged/system-verilog" class="post-tag" title="show questions tagged &#39;system-verilog&#39;" rel="tag">system-verilog</a> because it gives flexibility for verification and enforces best practices for RTL design. Quality design can be done with only <a href="/questions/tagged/verilog" class="post-tag" title="show questions tagged &#39;verilog&#39;" rel="tag">verilog</a>, however <a href="/questions/tagged/system-verilog" class="post-tag" title="show questions tagged &#39;system-verilog&#39;" rel="tag">system-verilog</a> will catch basic design bugs and syntheses surprises early (e.g. transparent latches, multiple drivers on nets, procedural when intending parallel logic).</p> <h3>Mission on StackOverflow (and Other StackExchange sites)</h3> <ul> <li>Help others</li> <li>Promote best practices</li> <li>Learn something new</li> </ul> <h3>Favorite Resources:</h3> <ul> <li>SystemVerilog LRM <a href="https://standards.ieee.org/findstds/standard/1800-2012.html" rel="nofollow noreferrer">IEEE Std 1800-2012</a> (includes legacy Verilog)</li> <li>UVM LRM <a href="https://standards.ieee.org/findstds/standard/1800.2-2017.html" rel="nofollow noreferrer">IEEE Std 1800.2-2017</a></li> <li><a href="http://www.sunburst-design.com/papers/" rel="nofollow noreferrer">Cliff Cummings Papers, Sunburst Design</a></li> <li><a href="http://www.sutherland-hdl.com/papers.html" rel="nofollow noreferrer">Stuart Sutherland Papers, Sutherland HDL</a></li> <li><a href="http://www.doulos.com/knowhow/sysverilog/" rel="nofollow noreferrer">Doulos Guide to SV</a></li> <li><a href="http://www.verilab.com/resources/papers-and-presentations/" rel="nofollow noreferrer">Verilab</a></li> <li><a href="https://www.edaplayground.com" rel="nofollow noreferrer">EDA Playground</a> (online simulator)</li> <li><a href="http://www.accellera.org/downloads/standards/uvm" rel="nofollow noreferrer">UVM</a> (Manual, User Guild, &amp; Code)</li> <li><a href="https://verificationacademy.com" rel="nofollow noreferrer">https://verificationacademy.com</a></li> <li><a href="http://cluelogic.com" rel="nofollow noreferrer">http://cluelogic.com</a></li> <li><a href="http://www.arm.com/files/pdf/Verilog_X_Bugs.pdf" rel="nofollow noreferrer">http://www.arm.com/files/pdf/Verilog_X_Bugs.pdf</a></li> </ul>
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      1. POSerial Testbenching and assertions with System-Verilog
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      1. POHow do you capture a group with regex?
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    1. COMove `integer i;` before `begin`. You cannot attach the file here directly. You can upload it to a file sharing site with public access (or your own personal site) and provide the link.
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      1. POIcarus Verilog simulation : Scope index expression is not constant: i
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    2. COI'm curious to see your approach. How does a fork-join help?
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    3. COI need to correct myself for the single quote for full queue assignment. Queues are apparently the exception as there are clear examples in [IEEE Std 1800-2012](http://standards.ieee.org/getieee/1800/download/1800-2012.pdf) section 7.10 Queues, but is allowed (10.10.3). Structure literals (5.10), array literals (5.10), unpacked arrays (7.4), dynamic arrays (7.5), and associative arrays(7.8) use `'{` for full assignments.
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