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USKrazy Glew
 

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    <p>Hacker, both hardware and software. Wannabe Agile team member.</p> <p>Although I probably contributed a lot to whatever processor you are using to read this on, I am a software guy at heart. HW guys call me a SW guy, SW guys call me a HW guy.</p> <p>In my copious free time I used to maintain a wiki on Computer Architecture, <a href="http://comp-arch.net" rel="nofollow noreferrer">http://comp-arch.net</a>. Will revive when job permits.</p> <p>C/C++ programmer - that's what HW simulators get written in. Perl, Python - that's what we analyze the results with.</p> <p>Code performance tuning. (Heck, not only did I contribute to the architecture of a large part of the CPU you are using, I may have done the same for the hardware that you use to measure performance on it.)</p> <p>Database: author of Perl SQL (not yet another interface to an SQL RDBMS - instead I implemented SQL to query experiment data in flat files). (You may still be able to find it on CPAN, although be kind, it was my first object oriented Perl (4?) code.) An early member of the NoSQL movement, although I am not so much against SQL, as I am against heavyweight databases with inflexible schema.</p> <p>Security: virtual machines, secure boot and patch; buffer overflows, code hijacking (ROP) prevention; cryptography performance optimization.</p> <p>Technology evangelist: XML, JSON.</p> <p>Wannabe user interface designer/programmer.</p> <p>Wannabe Agile team member: I love pair programming and test driven design, and want to do it in my day job.</p> <p>Domains: glew.net, glew.ca, comp-arch.net.</p> <p>Proud Canadian, hence domain glew.ca. US Permanent Resident, 20+ years in Portland, Oregon (and Illinois, and Silicon Valley, and Seattle area).</p> <p>DISCLAIMER:</p> <p>The content of my posts, whether on this website or anywhere else, are my personal opinion only. Although I am an employee (currently Nvidia; in the past of companies such as Imagination Technologies, MIPS, Intellectual Ventures/QIPS, Intel, AMD, Motorola, and Gould), I reveal this only so that the reader may account for any possible bias I may have towards my employers' products. The statements I make in no way represent my employers' positions on the issue, nor am I authorized to speak on behalf of my employers, past or present.</p>
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    2. POISO a version control tool that can manage files that are NOT under a directory tree marked as managed by the VC tool
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      1. POISO Mercurial "attributes" - tags that apply to more than one changeset, applied after the changeset
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      1. POemacs C/C++ indentation: different for pre and post comments // or: how can I make certain comments like //^ be indented extra?
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    1. CO... and use in a profile. Better yet, with PEBs you know where the (non-speculative) miss actually occurred.
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    2. COIndeed, Levinthal says no attribution. Unfortunate. But this is the way HW/SW codevelopment works: if the VTune guys provide software to do attribution by disabling cores and threads, then perhaps there will be justification for HW to do a better job next time. // BTW http://www.intel.com/Assets/en_US/PDF/designguide/323535.pdf says that you can do MEM_LOAD_RETIRED.LLC_MISS PEBS profiling, so there is yet another way to measure LLC misses.
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    3. CO// As for the hardware not allowing attribution of LLC misses to CPU - that's silly. Either VTune missed something or the HW missed obvious fixes: (a) there should be marking, and (b) the information is there in the hardware, since the cache miss must be routed back to the correct requesting CPU.
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