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    <p>These are probably not around in current (as of initial question) chips, but all have a common theme - atomic memory operations. Their purpose is typically for synchronisation between threads, and their inclusion at an instruction set level probably indicates that Atmel are planning to launch a multi-core AVR chip. Since they're specified now tool vendors can add them to assemblers already, but they won't make a big deal of that until chips have the instructions. (Edit: As it turns out, the other core is the USB peripheral, not a CPU. Thanks to avakar for that information.)</p> <p>The behaviour, as I read it from the <a href="http://www.atmel.com/images/Atmel-0856-AVR-Instruction-Set-Manual.pdf" rel="nofollow">Atmel AVR 8-bit Instruction Set Manual</a>:</p> <p>LAC - Load and Clear, loads memory contents *Z into register Rd while simultaneously clearing bits in *Z that were set in Rd. </p> <p>LAS - Load And Set simultaneously sets bits in a memory location that were set in a register, and loads the register with the prior contents of the memory location. Very useful for single-bit mutexes, for instance.</p> <p>LAT - Load And Toggle; like LAS, but instead of bitwise or, it uses bitwise xor, thus toggling bits. </p> <p>XCH - Exchange; simply exchanges memory and register contents. </p> <p>All of them are RAM access instructions (07/2014 reference states they take two cycles), which combine operations so they could also make code that needs RAM faster than it currently is. </p>
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    1. POMore detail about new AVR instructions LAC, LAS, LAT and XCH
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    1. USYann Vernier
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    1. COthese avr docs I have been combing through lately, both for my instruction set simulator and for programming the xmega via pdi, are loaded with typos and other mistakes. I assume the lac is missing ",Rd <- (Z)" at the end of the definition. It became a curiosity when I was making an instruction set simulator.
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    2. COmulti-core AVR? That would be super-awesome.
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      1. USStefan Paul Noack
    3. COI'm afraid the instructions were not added for another CPU core, but rather for the USB peripheral, which uses SRAM to store endpoint control/status registers. The instructions are missing in the early A and D models, but are present in AU and newer ones.
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