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POWhen L1 misses are a lot different than L2 accesses... TLB related?
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2011-12-12T13:31:19.700
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2016-09-29T10:27:04.583
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Body
I have been running some benchmarks on some algorithms and profiling their memory usage and efficiency (L1/L2/TLB accesses and misses), and some of the results are quite intriguing for me. Considering an inclusive cache hierarchy (L1 and L2 caches), shouldn't the number of L1 cache misses coincide with the number of L2 cache accesses? One of the explanations I find would be TLB related: when a virtual address is not mapped in TLB, the system automatically skips searches in some cache levels. Does this seem legitimate?
Tags
<caching><profiling><cpu-cache><tlb>
Title
When L1 misses are a lot different than L2 accesses... TLB related?
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1. PO
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1. USnuno
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