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POx86 cr3 and linux swqpper_pg_dir
 

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  1. POx86 cr3 and linux swqpper_pg_dir
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    <p>In linux source code(2.6.18):</p> <pre><code>movl $swapper_pg_dir-__PAGE_OFFSET,%eax movl %eax,%cr3 movl %cr0,%eax orl $0x80000000,%eax movl %eax,%cr0 /* ..and set paging (PG) bit */ ljmp $__BOOT_CS,$1f /* Clear prefetch and normalize %eip */ </code></pre> <p>And also the load_cr3(pgdir) and write_cr3(x) macro:</p> <pre><code>#define load_cr3(pgdir) write_cr3(__pa(pgdir)) #define write_cr3(x) \ __asm__ __volatile__("movl %0,%%cr3": :"r" (x)) </code></pre> <p>It seems like that the the whole cr3 control register store the address of Page Directory. However, when I reference the intel ia-32Developer's_Manual it tells a different story. The following is what the intel manual said:</p> <pre><code>name 0.............11 12.................31 cr3 flags address of page directory PDE flags address of page table PTE flags address of 4kb page frame </code></pre> <p>The manual says that the 20 MSB of cr3 stores the address of the page directory instead of the whole cr3 register. It is also reasonable since the page directory is exactly 4kb so the 12 LSB of the address is always zero. </p> <p>Isn't it a little bit strange cuz the linux code just assign the address of the page directory to the cr3 instead of the 20 MSB of the swapper_pg_dir.</p> <p>My question is that what exactly cr3 register is store, address or the format that intel manual suggest?</p> <p>The following link is the intel manual: <a href="http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html" rel="nofollow">http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html</a></p>
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    1. USmike820324
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    1. COSo, what is your question? You know, a sentence with, like, a question mark...
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    2. COsorry about that, I'll edit it.
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      1. USmike820324
 

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