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POmcr instruction after cache disable
 

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    1. PTQuestion
    1. USartless noise
    1. USkumar
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      1. VTUpMod
    1. COLook at the TRMs (technical reference manuals) for the specific core (make sure you get the rev number r2p0, etc even if it says it is obsolete) and l2 cache. If a read is marked as cacheable going into the L1 does it go out the L2 as cacheable or no? I think it does not, pretty trivial to test and find out. the mcr's should still perform there function, depends on the function, flushing a disabled or empty cache shouldnt do much should it? Invalidating will still do its job though, depends on the mcr. You need to provide more of these details
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      1. USold_timer
    2. COarm support in linux is a complete mess, tries to assume some commonality, actually whatever core was used by whomever checked it in is what is supported, the cache routines in particular are pretty bad and keep changing (not for the better). The TRM that matches the core rev and all is the authority, make your drivers/kernel match that TRM.
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      1. USold_timer
    3. COSorry,Maybe I have to rewrite the question - Ok, the question is Linux kernel provides an option to disable data cache through CONFIG_CPU_DCACHE_DISABLE and while tracing this macro I have seen using a "mcr" instruction to disable the cache. I have observed in drivers / kernel using dma_cache_maint routines. These routines endup in using mcr instruction to flush / invalidate. So, these routines doing flush/invalidate becomes NO-OP once CONFIG_CPU_DCACHE_DISABLE is enabled?
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      1. USkumar
 

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