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Slightly off-topic, but <ul> <li>in-order It depends on precisely what you mean by in-order! PowerPC has a variety of synchronizing instructions like like <code>sync</code>, <code>lwsync</code>, and <code>eieio</code> to enforce (different types of!) memory ordering, and <code>isync</code> which flushes the instruction pipeline. <a href="http://www.ibm.com/developerworks/systems/articles/powerpc.html" rel="nofollow">IBM has a decent summary</a>.</li> <li>risc processor I really wouldn't call the PPC "reduced" ;)</li> <li>stalls when branching IIRC, a correctly-predicted branch with its target in the instruction cache does not stall the G4 (I forget how the different models of G4 differ). OTOH, the G5 performs better if branch targets are 16-byte aligned (something about the branch target buffer).</li> <li>microcode instructions I thought half the point of RISC was to avoid microcode? I'm not aware of microcode updates, at any rate.</li> <li>load-hit-store problems when switching between float/int/vector representations I'm not sure what this means...</li> </ul> "Traditional" ARM might is probably closer to what you're looking for, but I suspect the more recent processors have some of the more "modern" processor features. My ARM box of choice is probably the SheevaPlug or similar, though the WZR-HP-G300NH router is cheaper (and comes with Wi-Fi) if you don't mind being constrained to 64 MB.
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1. POWhat's a good PPC based >MACHINE< for profiling code for in-order processors
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