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    <p>Read is fine. A 32-bit value is always read as a whole as long as it's not split on a cache line. Your align 8 guarantees that it's always within a cache line so you'll be fine.</p> <p>Forget about instructions reordering and all that non-sense. Results are always retired in-order. It would be a processor recall otherwise!!!</p> <p>Even for a dual CPU machine (i.e. shared via the slowest FSBs), you'll still be fine as the CPUs guarantee cache coherency via MESI Protocol. The only thing you're not guaranteed is the value you read may not be the absolute latest. BUT, what <em>is</em> the latest anyway? That's something you likely won't need to know in most situations if you're not writing back to the location based on the value of that read. Otherwise, you'd have used interlocked ops to handle it in the first place.</p> <p>In short, you gain nothing by using Interlocked ops on a read (except perhaps reminding the next person maintaining your code to tread carefully - then again, that person may not be qualified to maintain your code to begin with).</p> <p>EDIT: In response to a comment left by <strong>Adrian McCarthy</strong>.</p> <blockquote> <p>You're overlooking the effect of compiler optimizations. If the compiler thinks it has the value already in a register, then it's going to re-use that value instead of re-reading it from memory. Also, the compiler may do instruction re-ordering for optimization if it believes there are no observable side effects.</p> </blockquote> <p>I did not say reading from a non-volatile variable is fine. All the question was asking was if interlocked was required. In fact, the variable in question was clearly declared with <code>volatile</code>. Or were <em>you</em> overlooking the effect of the keyword <code>volatile</code>?</p>
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    1. POReading interlocked variables
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    1. USZach Saw
    1. USZach Saw
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    1. COThis is not quite correct. On x86 processors, reads are retired in order and writes are retired in order, but a write may be delayed after a subsequent read. Allowing this reordering is pretty much required to make a store buffer valuable.
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      1. USNeeraj Singh
    2. COOn a uArch level in the Northwood/Prescott CPU for example, there's a result forwarding mechanism in the uOp retiring unit that allows immediate consumption of result to the front-end, if its result is indeed what the front end is waiting for. No reordering can take place when it threatens the validity of the results (i.e. register/var dependencies). Worse, in the OP's case, there's no read following a write.
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      1. USZach Saw
    3. COYou're overlooking the effect of compiler optimizations. If the compiler thinks it has the value already in a register, then it's going to re-use that value instead of re-reading it from memory. Also, the compiler may do instruction re-ordering for optimization if it believes there are no observable side effects.
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      1. USAdrian McCarthy
 

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