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plurals
  1. POA DAG : Self referencing HASH: searching the first level parent from any level child and then search leaves of that parent
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    <p>I have netlist (collection of subcircuits) of circuit schematic, generally is created by some SPICE simulator. It generally has hierarchy (A top level subcircuit calls or instantiates different subcircuits and defines some connectivities amongst them through pins). A sample netlist looks like:</p> <pre><code>subckt AN2D0 A1 A2 VDD VSS Z M_u2 (net5 A2 VDD VDD) pch M_u1 (net5 A1 VDD VDD) pch M_u3 (Z net5 VDD VDD) pch M_u4 (net17 A2 VSS VSS) nch M_u2 (Z net5 VSS VSS) nch ends AN2D0 subckt LS_RX_CONTROLLER VDD VSS burst_start_or_sys burst_start_out pd pd_pwm_det pd_pwm_det_TII std_by std_by_or_sys sys_en sys_out I2 (burst_start_or_sys std_by VDD VSS burst_start_out) AN2D2 I1 (net22 std_by_bar VDD VSS sys_out) AN2D2 I5 (net022 pd VDD VSS pd_pwm_det) OR2D2 I10 (net026 pd VDD VSS std_by_or_sys) NR2D2 I9 (sys_en std_by VDD VSS net026) NR2D0 I6 (std_by VDD VSS std_by_bar) INVD0 I3 (pd_pwm_det_TII net037 VDD VSS net022) OR2D0 I11 (sys_en std_by VDD VSS net037) OR2D0 I0 (burst_start_or_sys sys_en VDD VSS net22) AN2D0 ends LS_RX_CONTROLLER </code></pre> <p>Now in different hierarchies same subcircuit can be instantiated. Every called subcircuit is defined before the calling subcircuit. This kind of graph is called Directed Acyclic GRAPH. I have made a self referencing HASH table from a netlist to save the space. If a subcircuit is calling some subcircuit instance it is then pointing the pin. At the very last hierarchy we will get a MOSFET D or S or G or B node (as the AN2D0 subcircuit has been defined). If any net (connection between to instances' pin) is brought out form the hierarchy (nothing but calling subcircuit, e.g. net5) to parent calling subcircuit it is called pin(e.g. Z) and will always be listed in the present subcircuit definition line followed by its name (<strong>subckt AN2D0 A1 A2 VDD VSS Z</strong>). I have created a hash of hashes of hashes.</p> <pre><code>GRAPH --&gt; subckt1---&gt;p1 p2 net1 net2 subckt2---&gt;p1 p2 net1 net2 subckt3---&gt;p1 ----&gt;I1.subckt1.p1---&gt;pointing to value of p1 key of subckt1. I2.subckt1.p2 p2 net1 net2 </code></pre> <p>For the present case the GRAPH looks like:</p> <pre><code>the name of subcircuit--&gt;AN2D0 name of pin or net--&gt;Z name of instant connected to it--&gt;M_u2.nch.D name of instant connected to it--&gt;M_u3.pch.D name of pin or net--&gt;VDD name of instant connected to it--&gt;M_u1.pch.S name of instant connected to it--&gt;M_u1.pch.B name of instant connected to it--&gt;M_u2.pch.S name of instant connected to it--&gt;M_u3.pch.S name of instant connected to it--&gt;M_u2.pch.B name of instant connected to it--&gt;M_u3.pch.B name of pin or net--&gt;A1 name of instant connected to it--&gt;M_u3.nch.G name of instant connected to it--&gt;M_u1.pch.G name of pin or net--&gt;VSS name of instant connected to it--&gt;M_u2.nch.S name of instant connected to it--&gt;M_u4.nch.B name of instant connected to it--&gt;M_u2.nch.B name of instant connected to it--&gt;M_u3.nch.B name of instant connected to it--&gt;M_u4.nch.S name of pin or net--&gt;net5 name of instant connected to it--&gt;M_u3.nch.D name of instant connected to it--&gt;M_u3.pch.G name of instant connected to it--&gt;M_u1.pch.D name of instant connected to it--&gt;M_u2.pch.D name of instant connected to it--&gt;M_u2.nch.G name of pin or net--&gt;A2 name of instant connected to it--&gt;M_u4.nch.G name of instant connected to it--&gt;M_u2.pch.G name of pin or net--&gt;net17 name of instant connected to it--&gt;M_u3.nch.S name of instant connected to it--&gt;M_u4.nch.D the name of subcircuit--&gt;LS_RX_CONTROLLER name of pin or net--&gt;burst_start_or_sys name of instant connected to it--&gt;I2.AN2D2.A1 M_u3.nch.G M_u1.pch.G name of instant connected to it--&gt;I0.AN2D0.A1 M_u3.nch.G M_u1.pch.G name of pin or net--&gt;burst_start_out name of instant connected to it--&gt;I2.AN2D2.Z M_u2.nch.D M_u3.pch.D name of pin or net--&gt;net037 name of instant connected to it--&gt;I11.OR2D0.Z M_u2.nch.D M_u3.pch.D name of instant connected to it--&gt;I3.OR2D0.A2 M_u3.nch.G M_u1.pch.G name of pin or net--&gt;net026 name of instant connected to it--&gt;I10.NR2D2.A1 M_u4.nch.G M_u2.pch.G name of instant connected to it--&gt;I9.NR2D0.ZN M_u3.nch.D M_u2.pch.D M_u4.nch.D name of pin or net--&gt;std_by name of instant connected to it--&gt;I9.NR2D0.A2 M_u3.nch.G M_u1.pch.G name of instant connected to it--&gt;I6.INVD0.I M_u3.pch.G M_u2.nch.G name of instant connected to it--&gt;I2.AN2D2.A2 M_u4.nch.G M_u2.pch.G name of instant connected to it--&gt;I11.OR2D0.A2 M_u3.nch.G M_u1.pch.G name of pin or net--&gt;sys_en name of instant connected to it--&gt;I11.OR2D0.A1 M_u4.nch.G M_u2.pch.G name of instant connected to it--&gt;I0.AN2D0.A2 M_u4.nch.G M_u2.pch.G name of instant connected to it--&gt;I9.NR2D0.A1 M_u4.nch.G M_u2.pch.G name of pin or net--&gt;VDD name of instant connected to it--&gt;I2.AN2D2.VDD M_u1.pch.S M_u1.pch.B M_u2.pch.S M_u3.pch.S M_u2.pch.B M_u3.pch.B name of instant connected to it--&gt;I10.NR2D2.VDD M_u1.pch.S M_u1.pch.B M_u2.pch.B name of instant connected to it--&gt;I0.AN2D0.VDD M_u1.pch.S M_u1.pch.B M_u2.pch.S M_u3.pch.S M_u2.pch.B M_u3.pch.B name of instant connected to it--&gt;I6.INVD0.VDD M_u3.pch.S M_u3.pch.B name of instant connected to it--&gt;I9.NR2D0.VDD M_u1.pch.S M_u1.pch.B M_u2.pch.B name of instant connected to it--&gt;I1.AN2D2.VDD M_u1.pch.S M_u1.pch.B M_u2.pch.S M_u3.pch.S M_u2.pch.B M_u3.pch.B name of instant connected to it--&gt;I11.OR2D0.VDD M_u1.pch.S M_u1.pch.B M_u3.pch.S M_u2.pch.B M_u3.pch.B name of instant connected to it--&gt;I3.OR2D0.VDD M_u1.pch.S M_u1.pch.B M_u3.pch.S M_u2.pch.B M_u3.pch.B name of instant connected to it--&gt;I5.OR2D2.VDD M_u1.pch.S M_u1.pch.B M_u3.pch.S M_u2.pch.B M_u3.pch.B name of pin or net--&gt;sys_out name of instant connected to it--&gt;I1.AN2D2.Z M_u2.nch.D M_u3.pch.D name of pin or net--&gt;net022 name of instant connected to it--&gt;I3.OR2D0.Z M_u2.nch.D M_u3.pch.D name of instant connected to it--&gt;I5.OR2D2.A1 M_u4.nch.G M_u2.pch.G name of pin or net--&gt;pd_pwm_det_TII name of instant connected to it--&gt;I3.OR2D0.A1 M_u4.nch.G M_u2.pch.G name of pin or net--&gt;std_by_or_sys name of instant connected to it--&gt;I10.NR2D2.ZN M_u3.nch.D M_u2.pch.D M_u4.nch.D name of pin or net--&gt;net22 name of instant connected to it--&gt;I0.AN2D0.Z M_u2.nch.D M_u3.pch.D name of instant connected to it--&gt;I1.AN2D2.A1 M_u3.nch.G M_u1.pch.G name of pin or net--&gt;pd name of instant connected to it--&gt;I10.NR2D2.A2 M_u3.nch.G M_u1.pch.G name of instant connected to it--&gt;I5.OR2D2.A2 M_u3.nch.G M_u1.pch.G name of pin or net--&gt;std_by_bar name of instant connected to it--&gt;I6.INVD0.ZN M_u2.nch.D M_u3.pch.D name of instant connected to it--&gt;I1.AN2D2.A2 M_u4.nch.G M_u2.pch.G name of pin or net--&gt;VSS name of instant connected to it--&gt;I11.OR2D0.VSS M_u3.nch.S M_u2.nch.S M_u4.nch.B M_u2.nch.B M_u3.nch.B M_u4.nch.S name of instant connected to it--&gt;I5.OR2D2.VSS M_u3.nch.S M_u4.nch.B M_u2.nch.S M_u2.nch.B M_u3.nch.B M_u4.nch.S name of instant connected to it--&gt;I3.OR2D0.VSS M_u3.nch.S M_u2.nch.S M_u4.nch.B M_u2.nch.B M_u3.nch.B M_u4.nch.S name of instant connected to it--&gt;I6.INVD0.VSS M_u2.nch.S M_u2.nch.B name of instant connected to it--&gt;I0.AN2D0.VSS M_u2.nch.S M_u4.nch.B M_u2.nch.B M_u3.nch.B M_u4.nch.S name of instant connected to it--&gt;I2.AN2D2.VSS M_u2.nch.S M_u4.nch.B M_u2.nch.B M_u3.nch.B M_u4.nch.S name of instant connected to it--&gt;I1.AN2D2.VSS M_u2.nch.S M_u4.nch.B M_u2.nch.B M_u3.nch.B M_u4.nch.S name of instant connected to it--&gt;I9.NR2D0.VSS M_u3.nch.S M_u4.nch.B M_u3.nch.B M_u4.nch.S name of instant connected to it--&gt;I10.NR2D2.VSS M_u3.nch.S M_u4.nch.B M_u3.nch.B M_u4.nch.S name of pin or net--&gt;pd_pwm_det name of instant connected to it--&gt;I5.OR2D2.Z M_u2.nch.D M_u3.pch.D </code></pre> <p>After this a subcircuit name and a pin of the same will be given which may be instantiated from any level hierarchy and we have to find the parent i.e. trace back the parent till the net has been pulled up as pin. And then stress back all the leaves(MOSFETS D or G or S or B pin).</p> <p>Please suggest what kind of algorithm will be best suitable for this and whether the storing them in a Self referencing hash table is efficient or not.</p>
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