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  1. POCompile multiple **changed** source files at once in GNU make
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    <p>I know there have been several questions with similar titles but none seem to provide an answer to what I need (correct me if I'm wrong).</p> <p>Consider this makefile:</p> <pre><code>SOURCES=file1.cpp file2.cpp file3.cpp OBJECTS=$(SOURCES:.cpp=.o) EXECUTABLE=myprog all: $(SOURCES) $(EXECUTABLE) $(EXECUTABLE): $(OBJECTS) $(CXX) -o $@ $(OBJECTS) file1.o: file1.cpp file1.h file2.o: file2.cpp file2.h file1.h file3.o: file3.cpp .cpp.o: $(CXX) $(CXXFLAGS) -c -o $@ $&lt; </code></pre> <p>If I change file1.h, the following is run:</p> <pre><code>g++ -c -o file1.o file1.cpp g++ -c -o file2.o file2.cpp g++ -o myprog file1.o file2.o file3.o </code></pre> <p>What I would like to have is:</p> <pre><code>g++ -c file1.cpp file2.cpp g++ -o myprog file1.o file2.o file3.o </code></pre> <p>(I know I can't specify object output directory with GCC, but this I can live with; it should be possible to work around with some <code>cd</code> commands.)</p> <p>In nmake, this is done with a double-colon inference rule (so-called called "<a href="http://msdn.microsoft.com/en-us/library/f2x0zs74.aspx">batch-mode rule"</a>). Basically, it groups the inference rules (e.g. ".obj.cpp:") for multiple targets and invokes the compiler for all dependencies instead of once per file. The <code>$&lt;</code> variable gets the list of dependencies instead of just the first one.</p> <p>Right now we're using parallel building (make -j) but it has its own issues, and VC++ compiler works much better in one-invocation mode so I'd prefer using that.</p>
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