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    <p>In brief, you can add the <code>ieee.numeric_std</code> package to your architecture (<code>library ieee; use ieee.numeric_std.all;</code>) and then do the addition using:</p> <pre><code>Output &lt;= std_logic_vector(unsigned(Output) + 1); </code></pre> <p>to convert your std_logic_vector to an unsigned vector, increment it, and finally convert the result back to an std_logic_vector.</p> <p>Note that if <code>Output</code> is an output port, this won't work because you can't access the value of an output port within the same block. If that is the case, you need to add a new signal and then assign <code>Output</code> from that signal, outside your process.</p> <p>If you do need to add a signal, it might be simpler to make that signal a different type than <code>std_logic_vector</code>. For example, you could use an integer or the <code>unsigned</code> type above. For example:</p> <pre><code>architecture foo of bar is signal Output_int : integer range 0 to (2**Output'length)-1; begin PR: process(clk, resetn) begin if resetn='0' then Output_int &lt;= 0; elsif clk'event and clk='1' then Output_int &lt;= Output_int + 1; end if; end process; Output &lt;= std_logic_vector(to_unsigned(Output_int, Output'length)); end foo; </code></pre> <p><code>Output_int</code> is declared with a range of valid values so that tools will be able to determine both the size of the integer as well as the range of valid values for simulation. In the declaration of <code>Output_int</code>, <code>Output'length</code> is the width of the <code>Output</code> vector (as an integer), and the "**" operator is used for exponentiation, so the expression means "all unsigned integers that can be expressed with as many bits as Output has".</p> <p>For example, for an <code>Output</code> defined as <code>std_logic_vector(31 downto 0)</code>, <code>Output'length</code> is 32. 2<sup>32</sup>-1 is the highest value that can be expressed with an unsigned 32-bit integer. Thus, in the example case, the <code>range 0 to (2**Output'length)-1</code> resolves to the range 0...4294967295 (2<sup>32</sup>=4294967296), i.e. the full unsigned range that can be expressed with 32 bits.</p> <p>Note that you'll need to add any wrapping logic manually: VHDL simulators will produce an error when you've reached the maximum value and try to increment by one, even if the synthesized logic will cleanly wrap around to 0.</p>
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    1. COWoah, that integer range thing blew me off the roof. Seems weird that you need this much to just add up one, but it does work as intended. Thanks for the explanation :)
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    2. COCould you explain range 0 to (2**Output'length)-1 ? I assume Output'length alone is 32 if my vector is 32 bits...
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    3. COYes, VHDL can be a bit obscure at times. :-) Output'length is the width of the Output vector (as an integer), and the "**" operator is used for exponentiation, so the expression means "all unsigned integers that can be expressed with as many bits as Output has".
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