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    <p><code>volatile</code> only forces your code to re-read the value, it cannot control where the value is read from. If the value was recently read by your code then it will probably be in cache, in which case volatile will force it to be re-read from cache, NOT from memory.</p> <p>There are not a lot of cache coherency instructions in x86. There are prefetch instructions like <a href="http://www.felixcloutier.com/x86/PREFETCHh.html" rel="nofollow noreferrer"><code>prefetchnta</code></a>, but that doesn't affect the memory-ordering semantics. It used to be implemented by bringing the value to L1 cache without polluting L2, but things are more complicated for modern Intel designs with a large shared <em>inclusive</em> L3 cache.</p> <p>x86 CPUs use a variation on the <a href="https://en.wikipedia.org/wiki/MESI_protocol" rel="nofollow noreferrer">MESI protocol</a> (MESIF for Intel, MOESI for AMD) to keep their caches coherent with each other (including the private L1 caches of different cores). A core that wants to write a cache line has to force other cores to invalidate their copy of it before it can change its own copy from Shared to Modified state.</p> <hr> <p>You don't need any fence instructions (like MFENCE) to produce data in one thread and consume it in another on x86, because x86 loads/stores have <a href="http://preshing.com/20120913/acquire-and-release-semantics/" rel="nofollow noreferrer">acquire/release semantics</a> built-in. You do need MFENCE (full barrier) to get sequential consistency. (A previous version of this answer suggested that <code>clflush</code> was needed, which is incorrect).</p> <p>You do need to prevent <a href="http://preshing.com/20120625/memory-ordering-at-compile-time/" rel="nofollow noreferrer">compile-time reordering</a>, because C++'s memory model is weakly-ordered. <code>volatile</code> is an old, bad way to do this; C++11 std::atomic is a much better way to write lock-free code.</p>
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    1. POCan I force cache coherency on a multicore x86 CPU?
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    1. POCan I force cache coherency on a multicore x86 CPU?
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    1. COWhat's the right order here then? _InterlockedExchange(); // atomic write _clflush() // sync caches _mfence() // cause a wait until caches synced Or do I need another _mfence() above the _clflush()? Thanks.
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    2. COAtomicWrite, Memory fence to wait for the AtomicWrite to hit the cache, CacheFlush, Memory Fence to make sure the next thing you write isn't visible until after the flush. This last fence may not be needed, I'm not sure.
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    3. COOkay, cool, I'll try that. Of course I have to wrap the whole thing in a conditional to determine whether _cflush exists, and since the whole thing should be packed tightly, I'm guessing I should just have an inline function that decides what to do based on a runtime system info class. Thanks!
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