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    <p>So, as far as I can make out, your different tests, or 'testcases' are in files named <code>test&lt;n&gt;.v</code>. And I'll assume that each of these testcases has a task that has the same name in all files, say <code>run_testcase</code>. This means that your testbench (<code>testbench.v</code>, say) must look something like:</p> <pre><code>module testbench(); ... `include "test.v" // &lt;- problem is this line ... initial begin // Some setup run_testcase(); // $finish; end endmodule </code></pre> <p>So your problem is the <code>include</code> line - a different file needs to be included depending on the testcase. I can think of two ways of solving this first one is as <strong>toolic</strong> suggested - using a symbolic link to 'rename' the testcase file. So an example wrapper script (<code>run_sim1</code>) to launch your sim might look a bit like:</p> <pre><code>#! /usr/bin/env sh testcase=$1 ln -sf ${testcase} test.v my_simulator testbench.v </code></pre> <p>Another way is to use a macro, and define this in the wrapper script for your simulation. Your testbench would be modified to look like:</p> <pre><code> ... `include `TESTCASE ... </code></pre> <p>And the wrapper script (<code>run_sim2</code>):</p> <pre><code>#! /usr/bin/env sh testcase=$1 my_simulator testbench.v +define+TESTCASE=\"${testcase}\" </code></pre> <p>The quotes are important here, as the verilog <code>include</code> directive expects them. Unfortunately, we can't leave the quotes in the testbench because it will then look like a string to verilog, and the <code>TESTCASE</code> macro won't be expanded.</p>
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