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POSimple VHDL 4 to 1 MUX testbench is hanging
 

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  1. POSimple VHDL 4 to 1 MUX testbench is hanging
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    <pre><code> -----------begin part1.vhdl--------------------- library ieee; use ieee.std_logic_1164.all; entity part1 is generic ( width : integer :=7); PORT( a, b, c, d: IN std_logic_vector(width downto 0); sel: IN std_logic_vector(1 downto 0); result: OUT std_logic_vector(width downto 0) ); end part1; architecture muxbehav of part1 is BEGIN result &lt;= a after 5 ns when sel="00" else b after 5 ns when sel="01" else c after 5 ns when sel="10" else d after 5 ns; end muxbehav; -----------end part1.vhdl--------------------- -----------begin part1_tb.vhdl------------------ library ieee; use ieee.std_logic_1164.all; entity part1_tb is generic( width : integer := 7); end part1_tb; architecture tb of part1_tb is signal t_a: std_logic_vector(width downto 0):="00000000"; signal t_b: std_logic_vector(width downto 0):="00000000"; signal t_c: std_logic_vector(width downto 0):="00000000"; signal t_d: std_logic_vector(width downto 0):="00000000"; signal t_s: std_logic_vector(1 downto 0); signal t_o: std_logic_vector(width downto 0); component part1 generic(width : integer); PORT( a, b, c, d: IN std_logic_vector(width downto 0); sel: IN std_logic_vector(1 downto 0); result: OUT std_logic_vector(width downto 0) ); end component; begin U_part1: part1 generic map(width) port map(a=&gt;t_a, b=&gt;t_b, c=&gt;t_c, d=&gt;t_d, sel=&gt;t_s, result=&gt;t_o); process begin t_a &lt;= "11111111"; t_b &lt;= "00000001"; t_c &lt;= "10101010"; t_d &lt;= "01010101"; wait for 10 ns; t_s &lt;= "00"; wait for 6 ns; assert (t_o="11111111") report "Error input a" severity error; wait for 10 ns; t_s &lt;= "01"; wait for 6 ns; assert (t_o="00000001") report "Error input b" severity error; wait for 10 ns; t_s &lt;= "10"; wait for 6 ns; assert (t_o="10101010") report "Error input c" severity error; wait for 10 ns; t_s &lt;= "11"; wait for 6 ns; assert (t_o="01010101") report "Error input d" severity error; wait; end process; end tb; -----------end part1_tb.vhdl------------------ </code></pre> <p>Hello, this is my first code I've written in VHDL. It's a simple 4 to 1 MUX that can take in a vector of any width. However, when I try running my testbench, GHDL just hangs. I've looked at testbenches similar to mine, but I still cannot find why mine is hanging. Any ideas?</p>
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    1. USDrew
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    1. COBy "hang", do you mean the simulation is just running without anything happening, or the simulation time just stops advancing?
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      1. USTomi Junnila
    2. COCan you post your platform details and version of GHDL? And your compile/run commands?
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      1. POSimple VHDL 4 to 1 MUX testbench is hanging
      1. USMartin Thompson
    3. COwhat does the "wait" at the end of the process do? Is it forcing it to stop? Sorry I don't know VHDL that well..more of a Verilog person.
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      1. POSimple VHDL 4 to 1 MUX testbench is hanging
      1. USuser623879
 

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