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    <p>TTAS (#2) is good practice. "Lurking" and waiting for the "opportunity" before doing <code>CAS</code> is common practice in both Java and .NET concurrent classes. With that said, <code>cmpxchg</code> received quite a lot of optimizations in the last few years, so it might be possible that you'd get nearly identical results on the latest crop of processors.</p> <p>What you should try in both cases, however is to employ some <a href="http://www.cs.brown.edu/courses/cs176/ch07.ppt" rel="nofollow">exponential backoff</a> when you spin.</p> <p><strong>Update</strong></p> <p>@GJ: You should find <a href="http://software.intel.com/en-us/articles/implementing-scalable-atomic-locks-for-multi-core-intel-em64t-and-ia32-architectures/?wapkw=%28Implementing+Scalable+Atomic+Locks+Multi%29" rel="nofollow">some more up-to-date documentation on Intel's site</a>. Note the paragraph about not locking the bus since 486 and the comparison chart of <code>xchg</code> and <code>cmpxchg</code> that shows that they are practically identical. </p> <p>Spinning on a read vs on a <code>locked</code> instruction will still be a good idea to avoid some contention on getting the cache line in exclusive mode. (So TTAS.)</p> <p>However this will provide a useful gain only if you implement e.g. an exponential back-off, even yielding the CPU after a while. </p> <p>The differences between TTAS and TAS, or w/o backoff would be smaller if you are using a single, modern multi-core CPU with a shared L3 cache between the cores and would become more visible if you are using a multi-socket - e.g. server - machine or a multi-core CPU that has no shared cache between the cores. They would also be different based on the amount of contention. (I.e. light load would see smaller difference between TTAS/TAS.)</p>
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