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    <p><strong>High Resolution, Low Overhead Timing for Intel Processors</strong></p> <p>If you're on Intel hardware, here's how to read the CPU real-time instruction counter. It will tell you the number of CPU cycles executed since the processor was booted. This is probably the finest-grained counter you can get for performance measurement.</p> <p>Note that this is the number of CPU cycles. On linux you can get the CPU speed from /proc/cpuinfo and divide to get the number of seconds. Converting this to a double is quite handy.</p> <p>When I run this on my box, I get</p> <pre><code>11867927879484732 11867927879692217 it took this long to call printf: 207485 </code></pre> <p>Here's the <a href="http://cs.smu.ca/~jamuir/rdtscpm1.pdf" rel="noreferrer">Intel developer's guide</a> that gives tons of detail.</p> <pre><code>#include &lt;stdio.h&gt; #include &lt;stdint.h&gt; inline uint64_t rdtsc() { uint32_t lo, hi; __asm__ __volatile__ ( "xorl %%eax, %%eax\n" "cpuid\n" "rdtsc\n" : "=a" (lo), "=d" (hi) : : "%ebx", "%ecx"); return (uint64_t)hi &lt;&lt; 32 | lo; } main() { unsigned long long x; unsigned long long y; x = rdtsc(); printf("%lld\n",x); y = rdtsc(); printf("%lld\n",y); printf("it took this long to call printf: %lld\n",y-x); } </code></pre>
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    1. POIs gettimeofday() guaranteed to be of microsecond resolution?
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    1. USEvan Teran
    1. USMark Harrison
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    1. CONote that the TSC might not always be synchronized between cores, might stop or change its frequency when the processor enters lower power modes (and you have no way of knowing it did so), and in general is not always reliable. The kernel is able to detect when it is reliable, detect other alternatives like HPET and ACPI PM timer, and automatically select the best one. It's a good idea to always use the kernel for timing unless you are really sure the TSC is stable and monotonic.
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    2. COThe TSC on Core and above Intel platforms is synchronized across multiple CPUs *and* increments at a constant frequency independent of power management states. See Intel Software Developer’s Manual, Vol. 3 Section 18.10. However the rate at which the counter increments is *not* the same as the CPU's frequency. The TSC increments at “the maximum resolved frequency of the platform, which is equal to the product of scalable bus frequency and maximum resolved bus ratio” Intel Software Developer’s Manual, Vol. 3 Section 18.18.5. You get those values from the CPU's model-specific registers (MSRs).
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    3. COYou can obtain the scalable bus frequency and maximum resolved bus ratio by querying the CPU’s model-specific registers (MSRs) as follows: Scalable bus frequency == MSR_FSB_FREQ[2:0] id 0xCD, Maximum resolved bus ratio == MSR_PLATFORM_ID[12:8] id 0x17. Consult Intel SDM Vol.3 Appendix B.1 to interpret the register values. You can use the msr-tools on Linux to query the registers. http://www.kernel.org/pub/linux/utils/cpu/msr-tools/
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