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    <p>That's not a simple task in ARM assembly because you can't easily use 32 bit constants. You have to break up all your operations that mask out bytes to use 8 bit constants each (also these constants can be rotated).</p> <p>You mask out byte2 and 3 using the AND instruction and do the shift later. in ARM-assembler you have with most instruction one shift for free, so the shift-into-position and merge with the other bits often end up being a single instruction.</p> <p>Here is some untested code that does the middle byte swap (ARMv4, not thumb-instruction set):</p> <pre><code> .text swap_v4: AND R2, R0, #0x00ff0000 @ R2=0x00BB0000 get byte 2 AND R3, R0, #0x0000ff00 @ R3=0x0000CC00 get byte 1 BIC R0, R0, #0x00ff0000 @ R0=0xAA00CCDD clear byte 2 BIC R0, R0, #0x0000ff00 @ R0=0xAA0000DD clear byte 1 ORR R0, R2, LSR #8 @ R0=0xAA00BBDD merge and shift byte 2 ORR R0, R3, LSL #8 @ R0=0xAACCBBDD merge and shift byte 1 B LR </code></pre> <p>That translate line by line into the following c-code:</p> <pre><code>int swap (int R0) { int R2,R3; R2 = R0 &amp; 0x00ff0000; R3 = R0 &amp; 0x0000ff00; R0 = R0 &amp; 0xff00ffff; R0 = R0 &amp; 0xffff00ff; R0 |= (R2&gt;&gt;8); R0 |= (R3&lt;&lt;8); return R0; } </code></pre> <p>You'll see - lots of lines for such a simple task. Not even the ARMv6 architecture helps here much. </p> <hr> <p>EDIT: ARMv6 version (also untested, but two instructions shorter)</p> <pre><code>swap_v6: @ bits in R0: aabbccdd ROR R0, R0, #8 @ r0 = ddaabbcc REV R1, R0 @ r1 = ccbbaadd PKHTB R0, R0, R1 @ r0 = ddaaccbb ROR R0, R0, #24 @ r0 = aaccbbdd BX LR </code></pre>
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