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    <p>Consider the following scenario - this is the critical case where speculative load execution can theoretically harm sequential consistency</p> <p>initially [x]=[y]=0</p> <pre><code>CPU0: CPU1: store [x]&lt;--1 store [y]&lt;--1 load r1&lt;--[y] load r2&lt;--[x] </code></pre> <p>Since x86 allows loads to be reordered with earlier stores to different addresses, both loads may return 0's. Adding an lfence alone after each store wouldn't prevent that, since they only prevent reordering within the same context, but since stores are dispatched after retirement you can have both lfences and both loads commit before the stores are performed and observed.</p> <p>An <strong>mfence</strong> on the other hand would force the stores to perform, and only then allow the loads to be executed, so you'll see the updated data on at least one context.</p> <p>As for <strong>sfences</strong> - as pointed out in the comment, in theory it's not strong enough to prevent the load from reordering above it, so it might still read stale data. While this is true as far as the memory official ordering rules apply, I believe that current implementation of x86 uarch makes it slightly stronger (while not committing to do so in the future, I guess). According to <a href="http://www.realworldtech.com/haswell-tm-alt/2/" rel="noreferrer">this description</a>:</p> <blockquote> <p>Because of the strong x86 ordering model, the load buffer is snooped by coherency traffic. A remote store must invalidate all other copies of a cache line. If a cache line is read by a load, and then invalidated by a remote store, the load must be cancelled, since it potentially read invalid data. The x86 memory model does not require snooping the store buffer.</p> </blockquote> <p>Therefore, any load not yet committed in the machine should be snoopable by stores from other cores, thereby making the <strong>effective</strong> observation time of the load at the <strong>commit</strong> point, and not the <em>execution</em> point (which is indeed out of order and may have been performed much earlier). Commit is done in order, and therefore the load should be observed after previous instructions - making lfences pretty much useless as I said above in the comments, since the consistency can be maintained the same way without them. This is mostly speculation, trying to explain the common conception that lfences are meaningless in x86 - I'm not entirely sure where it originated and if there are other considerations at hand - would be happy for any expert to approve / challenge this theory.</p> <p><em>All the above applies only for WB mem types of course</em></p>
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    1. PODoes it make any sense to use the LFENCE instruction on x86/x86_64 processors?
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      1. VTUpMod
    1. COSFENCE cannot be used to fix this example, because a load can migrate up across SFENCE. The example requires MFENCE to fix.
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      1. USArch D. Robison
    2. CO@ArchD.Robison, in practice, the load would have to retire after any previous instruction, and during that time a store from the other thread would be able to snoop it - I think this would cause re-execution but i'm not entirely sure, so I fixed the answer as you suggested - thanks.
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    3. COThanks for the fix. I recommend coding against the architectural guarantees since the micro-architects are always looking for clever and mysterious ways to speed things up.
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