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    <p><a href="https://groups.google.com/forum/#!search/mashey%2420jthill/comp.arch/JmLV5AaF3Nc/Cf2UyFikauwJ" rel="nofollow">I asked this on comp.arch some time ago and got some really good answers</a>, leading off with this from Dr. Mashey:</p> <blockquote> <p>|> I have wondered whether using all that FP space for another three or<br> |> four integer units and supplying hand-tuned FP libs for each model would<br> |> pay for itself, but I've always figured that if that could be made to<br> |> pay, the designers would have done it. Perhaps now that superscalar is<br> |> the order of the day, it'll be done soon. </p> <p>1) FP hardware is there, because if you care about FP performance at<br> all, it is very difficult to emulate the required behavior with typical<br> integer operations at a reasonable speed. These days, typical<br> FP add/mul are ~2-3 clocks latency, with 1-cycle repeat rates. </p> <p>2) There is, of course, substantial experience in the microprocessor<br> world of people supplying libraries to do FP withotu an FP unit,<br> for systems where FP use was expected to be infrequent, or where<br> the FP coprocessor wasn't yet available. This has been true for<br> X86s, 68KS, and MIPS, among others. In MIPS' case:<br> (a) There were systems with R2000s by themselves.<br> (b) Then there was a big coprocessor board.<br> (c) Finally, the R2010 FPU came out, and fairly rapidly, most<br> systems had both R2000 &amp; R2010. In the embedded markets, there<br> are many uses for CPUs without FPUs still. </p> <p>3) Put another way: to any competitors: it is really a cool idea to<br> drop the hardware FP and emulate via integer ops :-) </p> </blockquote>
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    1. POHave there been attempts to represent floats with unsigned or signed integers?
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    1. COthanks I'll take a look into that
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    2. COas a comment to this post, I should also say that the hardware support for the FPU in the ARM world is a quite recent discovery, especially if we consider the whole pair hardware+kernel .
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