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    <p>The ARM versions of these are in <a href="https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/include/asm/io.h" rel="nofollow"><em>arch/arm/include/asm/io.h</em></a>. The <code>iowrite32</code> macros will ultimately call these. You can look at an implementation for 32bits.</p> <pre><code>static inline void __raw_writel(u32 val, volatile void __iomem *addr) { asm volatile("str %1, %0" : "+Qo" (*(volatile u32 __force *)addr) : "r" (val)); } </code></pre> <p>There is an <em>ARMv5+</em> instruction called <a href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0068b/Chdggchb.html" rel="nofollow"><code>strd</code></a> which takes two registers and writes them. It is possible if you BUS structure is configured properly that it will run this as a single cycle. However, you need to have many other things setup properly. The MMU permissions for the I/O page as well as physical/FPGA connection of the ARM AXI to your FPGA device.</p> <p>There are no public gcc constraints for a 64bit ARM assembler values. As the calling convention puts them in <code>r0</code> and <code>r1</code> we can make the function never inline.</p> <pre><code>static noinline void __raw_write64(u64 val, volatile void __iomem *addr) { register u32 v1 asm ("r0") = val &gt;&gt; 32; register u32 v2 asm ("r1") = val &amp; 0xfffffffUL; asm volatile("strd r0, %0" : "+Qo" (*(volatile u64 __force *)addr) : "r" (v1), "r" (v2)); } </code></pre> <p>This is at least generating good code with <em>objdump</em>, but you might need to polish it for production quality.</p> <p>That is at least the code needed. I think that the device memory should be non-cacheable and non-bufferable by default. You may need barrier type instructions as well.</p>
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    1. POUse 32bit ops to perform ioread/write64
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    1. COSee also [STM on ARM](http://stackoverflow.com/questions/15500308/for-arm-why-a-single-stm-instruction-is-generally-faster-than-multiple-str-inst). You may also be able to use `unsigned long long*` for the peripheral address. Basically, `write64()` is not a standard Linux API afaik. The inline assembler gives more control, especially if you need barrier, etc.
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    2. COThanks. we able to read 64bit from logram. But when we use "r0" and "r1" it seem like only able to read only 1 32bit data anther seem to be overwrite why?. function of "+Qo"?
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    3. COSorry, I don't completely understand. Did the write work, but you can't get read to work? The syntax should be `asm("ldrd r0,%2\n" : "+Qo" pointer, "=r" (v1), "=r" (v2) );` with the `v1` and `v2` grouped with the first one (no colon). The compiler may overwrite your registers otherwise. If this doesn't work, but `strd` does, then I would suspect your hardware interface.
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