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    <p>Though this is not going to be the best answer, iw ould like to share my thoughts on confused points.</p> <p><code>1.</code> Does Page table is maintained...</p> <p>Yes. kernel maintains the page tables. In fact it maintains nested page tables. And top of the page tables is stored in top_pmd. pmd i suppose it is page mapping directory. You can traverse through all the page tables using this structure.</p> <p><code>2.</code> How MMU cannot find the address in physical RAM.....</p> <p>I am not sure i understood the question. But in case because of some problem, the instruction is faulted or out of its instruction area is being accessed, you generally get undefined instruction exception resulting in undefined exception abort. If you look at the crash dumps, you can see it in the kernel log.</p> <p><code>3.</code> Is the Mapping table - virtual to physical is inside a MMU...</p> <p>Yes. MMU is SW+HW. HW is like TLB and all. The mapping tables are stored here. For instructions, that is for code section i always converted the physical-virtual address and always they matched. And almost all the times it matches for Data sections as well.</p> <p><code>4.</code> cat /proc/pid_value/maps. This shows me the current mapping of the vmarea....</p> <p>This is more used for analyzing the virtual addresses of user space stacks. As you know virtually all the user space programs can have 4 GB of virtual address. So unlike kernel if i say 0xc0100234. You cannot directly go and point to the istruction. So you need this mapping and the virtual address to point the instruction based on the data you have.</p> <p><code>5.</code> The high-mem concept is that kernel cannot directly access the Memory...</p> <p>High-mem corresponds to user space memory(some one correct me if i am wrong). When kernel wants to read some data from a address at user space you will be accessing the HIGHMEM.</p> <p><code>6.</code> Does the processor specifically comes with the MMU support. Those who doesn't have MMU support cannot run LInux?</p> <p>MMU as i mentioned is HW + SW. So mostly it would be coming with the chipset. and the SW would be generally architecture dependent. You can disable MMU from kernel config and build. I have never tried it though. Mostly these days allthe chipsets have it. But small boards i think they disable MMU. I am not entirely sure though.</p> <p>As all these are conceptual questions, i may be lacking some knowledge and be wrong at places. If so others please correct me.</p>
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    1. PODoes Virtual Memory area struct only comes into picture when there is a page fault?
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    1. COThanks!I will elaborate the 2nd point more. Let's say the virtu addr is 0xc0100234. This should be translated to physical memory addr.I hope that this is based on the calculation 12-bit shift + offset.This may be an invalid addr but still my be a valid addr for another process.This means MMU can access this.How MMU determines that it is wrong addr for this addr. It is actually a valid addr. All the process should have a unique Virt addr if the formula to convert VA to PA is same. But this is not true. How does it happen? the process can have the same VA but still translates to different addr.
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    2. CO0xc0100234 -> 0x100234(Physical address). Y do you think this is invalid address? It is definetely in the DDR ram space. I am talking all this about linux kernel space. In User space, you have something called space id:s which are used for mapping cirtual addresses by MMU. So in user space, 0xd1234567 is mapped as <PID>:0xd1234567. This way it differentiates.
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    3. COOk, I was looking for this part - So in user space, 0xd1234567 is mapped as <PID>:0xd1234567. This way it differentiates. So, you say MMu maintains the address like the following - <PID>:address. I am not convinced with it. In memory layer- we talk about just an address. How the final address differs is the question?what this translates to <PID>:0xd1234567 and what this translates to <PID_UN>:0xd1234567. how this is calculated? Do MMU speaks to Kernel to get the address from pid+ VA. It cannot be right? Because we have that 12-bit shift logic.
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