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2013-11-06T19:09:36.150
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There actually are two issues here: (1) On what you are trying to build; (2) On the code itself. 1) On what you are trying to build: You are trying to build a T-type flip-flop. This is usually built with a D-type flip-flop by simply connecting an inverted version of its output back to its input. In your case, you also want a "toggle enable" signal (called T in your code), to allow stopping the TFF when T=0. This means that the TFF input must go through an XOR gate, nothing else. Such XOR gate can be constructed as you did (AND-OR layers) or using directly an XOR gate. Because the DFFs in FPGAs are already constructed with an enable port (XOR functionality internal to the DFF), it is better to use the XOR option, saving logic and operating faster. But the other option will also function, obviously. 2) Regarding the code: <ul> <li>Q is buffer, not inout</li> <li>Include "and clk='1'" (-> rising_edge(clk))</li> <li>Eliminate variables hold1, hold2</li> <li>Use Q <= T xor Q instead of Q <= (T and notQ) or (not T and Q)</li> </ul> <hr> <pre><code>library ieee; use ieee.std_logic_1164.all; -------------------------------------------- entity T_FF is port ( T, clk: in std_logic; Q : buffer std_logic); end T_FF; -------------------------------------------- architecture behv of T_FF is begin process (clk) is begin if rising_edge(clk) then Q <= (T and not Q) or (not T and Q); --Q <= T xor Q; --preferred option end if; end process; end behv; -------------------------------------------- </code></pre>
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