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POVHDL Define a signal when undefined
 

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    <p>So, I've been working on some VHDL homework and I'm having some trouble with my testbench. Basically, my testbench is running through the different possibilities for a number of flip-flops. However, I keep getting 'U' as a result from one of the flip-flops, and while I know exactly why, I have no idea how to fix it. </p> <p>Basically, what is happening is that for my T flip-flop, since Q isn't set when I perform the XOR operation, the program never ends up assigning a value to Q after the XOR operation. So basically, I need a way of setting Q to, say, 0, iff Q has not been defined.</p> <p>Just for reference, here is my code for the T-flipflop</p> <pre><code>library ieee; use ieee.std_logic_1164.all; entity T_FF is port ( T, clk : in std_logic; Q : inout std_logic); end T_FF; architecture behv of T_FF is begin process (clk) is variable hold1, hold2 : std_logic; begin if (clk'event) then hold1 := Q and (not T); hold2 := T and (not Q); Q &lt;= hold1 or hold2; end if; end process; end behv; </code></pre> <p>And the testbench:</p> <pre><code>library ieee; use ieee.std_logic_1164.all; entity tb is end tb; architecture behv of tb is -- Component declaration component T_FF is port ( T, clk : in std_logic; Q : inout std_logic); end component; signal sT : std_logic :='0'; signal sclk : std_logic :='0'; signal sQT : std_logic :='0'; for TFF : T_FF use entity work.T_FF(behv); begin TFF: T_FF port map (T=&gt;sT, clk=&gt;sclk, Q=&gt;sQT); sclk &lt;= not sclk after 50 ns; sT &lt;= not sT after 100 ns; end; </code></pre>
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    1. USCameron Simpson
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    1. COWelcome to Stack Overflow! Your question might be better suited on http://electronics.stackexchange.com/, one of our sister sites.
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      1. USChris Laplante
 

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