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    <p>The principle of separate address bus width (ADDRWIDTH) and number of RAM entries (DATADEPTH) is fine, and would give the synthesis tool freedom to implement the design without using more RAM bits than required.</p> <p>The reason that you may see more RAM bits used than minimum required, is that the synthesis tool may choose an implementation that uses more internal RAM primitives than the absolute minimum, which will usually occur if the there are plenty of free RAM primitives or if so required in order to close timing.</p> <p>If you try to experiment with the settings of DATAWIDTH, DATADEPTH, and ADDRWIDTH, you will see that the synthesis tool does indeed use fewer internal RAM primitives than what a simple rounding up of DATADEPTH to new 2 ** N would require.</p> <p>Using DATAWIDTH = 72, DATADEPTH = 17 * 1024, and ADDRWIDTH = 16 requires a minimum of 72 * 17 Kib = 1224 Kib. In one synthesis trial, this can fit into 76 RAMB16 of a Spartan6, thus total of 76 * 18 Kib = 1368 Kib. Figure from synthesis is below.</p> <p><img src="https://i.stack.imgur.com/YAz49.jpg" alt="enter image description here"></p> <p>If DATADEPTH was rounded to nearest 2 * boundary it would be 32 * 1024, thus requiring 72 * 32 Kib = 2304 Kib. So the Xilinx synthesis tool does make an intelligent fit.</p> <p>By the way then a signal should be used for RAM, and not a shared variable, since I expect that a shared variable may cause problems in some synthesis tools.</p> <p>Suggestion for code, including use clauses:</p> <pre><code>library ieee; use ieee.std_logic_1164.all; entity foo is generic ( DATAWIDTH : positive := 72; DATADEPTH : positive := 17 * 1024; ADDRWIDTH : positive := 16 ); port ( clk_a : in std_logic; we_a : in std_logic; addr_a : in std_logic_vector(ADDRWIDTH-1 downto 0); di_a : in std_logic_vector(DATAWIDTH-1 downto 0); do_a : out std_logic_vector(DATAWIDTH-1 downto 0) ); end foo; library ieee; use ieee.std_logic_unsigned.all; architecture bar of foo is type myram_type is array (DATADEPTH-1 downto 0) of std_logic_vector(DATAWIDTH-1 downto 0); --! type for ram content signal myram : myram_type; --! ram begin process (clk_a) begin if rising_edge(clk_a) then if we_a = '1' then myram(conv_integer(addr_a)) &lt;= di_a; end if; do_a &lt;= myram(conv_integer(addr_a)); end if; end process; end bar; </code></pre>
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    1. POInferring BRAM with unused addresses efficiently
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    1. USMorten Zilmer
    1. USMorten Zilmer
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    1. POInferring BRAM with unused addresses efficiently
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    1. VO
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      1. VTUpMod
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    1. COThanks a lot for sharing your observations and the suggested code! I'll give it a shot asap.
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