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    <p>The single process form is simpler and shorter. This alone reduces the chance that it contains errors.</p> <p>However the fact that it also eliminates the "incomplete sensitivity list" problem that plagues the other's combinational process <strong>should</strong> make it the clear winner regardless of any other considerations.</p> <p>And yet there are so many texts and tutorials advising the reverse, without properly justifying that advice or (in at least one case I can't find atm) introducing a silly mistake into the single process form and rejecting the entire idea on the grounds of that mistake.</p> <p>The <em>only</em> thing (AFAIK) the single-process form doesn't do well is un-clocked outputs. These are (IMO) poor practice anyway as they can be races at the best of times, and could be handled by a separate combinational process <em>for that output only</em> if you really had to.</p> <p>I'm guessing there was originally some practical reason behind it; maybe a mid-1990s synthesis tool that couldn't reliably handle the single process form, and that made it into the original documentation that the lecturers learned from. Like those blasted non-standard <code>std_logic_arith</code> libraries. And so the myth has been perpetuated...</p> <p>Those same lecturers would probably have a fit if they saw what can pass through a modern synthesis tool : integers, enumerations, record types, loops, functions and procedures updating signals (Xilinx ISE is now fine with these. Some versions of Synplicity have trouble with functions, but accept an identical procedure with an Out parameter).</p> <p>One other comment : I prefer <code>if Rst = '1' then</code> over <code>if (Rst = '1') then</code>. It looks less like line noise (or C).</p>
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    1. COHow about going one step further and writing just `if Rst then`? It is even cleaner (better signal/noise ratio)
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    2. COYes absolutely, if you get to define the type of the Rst signal! People often forget that Boolean is synthesisable too. Unfortunately you may be given a situation where - especially external connections like Rst - are std_logic, or coding standards insist it must be, and then you have to make the explicit comparison.
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    3. COI like boolean signals too, but I wanted to point that `if Rst then ...` will work even if `Rst` is of type `std_logic` in VHDL 2008. It's amazing how much this trick can clean up some expressions.
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