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    <p>I'm trying to build a simple pulse generator for a CPLD in VHDL. I have a series of simple <em>if</em> statements that should perform certain tasks depending on the input state of a bus connected to the module.</p> <pre><code>entity pulse_gen is Port ( CLK : in STD_LOGIC; pulse_sel_in : in STD_LOGIC_VECTOR (2 downto 0); pulse_r : in STD_LOGIC; pulse_s : inout STD_LOGIC); end pulse_gen; architecture Behavioral of pulse_gen is signal pulse_sel: std_logic_vector (2 downto 0); signal pulse_count: integer; signal pulse_length: integer range 0 to 100; signal pulse_a: std_logic; begin pulse_sel &lt;= pulse_sel_in; pulse: process(CLK) is begin if(pulse_sel &gt; "000" and pulse_a = '0') then pulse_s &lt;= '1'; pulse_a &lt;= '1'; end if; if(pulse_a = '1' and pulse_count &lt; pulse_length) then pulse_count &lt;= pulse_count + 1; end if; if(pulse_a = '1' and pulse_count = pulse_length) then pulse_s &lt;= '0'; pulse_a &lt;= '0'; pulse_count &lt;= 0; end if; end process; set_max: process(CLK) is begin if (CLK'event) then case pulse_sel is when "001" =&gt; pulse_length &lt;= 1; when "010" =&gt; pulse_length &lt;= 10; when "011" =&gt; pulse_length &lt;= 100; when others =&gt; null; end case; end if; end process; end Behavioral; </code></pre> <p>When running this module in iSim, forcing the _pulse_s_ bus to anything but 000 should trigger the first if statement in the pulse process, which it does. However, in the simulation, the _pulse_a_ signal is never set to logic high. Now I have spent hours writing this module in different ways, but I have absolutely no idea why this doesn't happen. I'm relatively new to VHDL, so I wonder if there's some kind of syntax or procedural error that I'm just completely missing. Any ideas?</p>
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