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19061734
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2013-09-27T23:52:52.677
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2013-10-01T23:57:57.123
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The stalls in cases 2 and 3 come from the second instruction depending in its first ALU stage on the result of the load in the previous instruction (which is not available until after the second Data Memory stage, so the stall if for the earlier instruction's second ALU stage and the two Data Memory stages). (L8 of the first instruction lines up with L4 of the second.) <pre><code> L1-->IF-->L2-->DE-->L3-->RR-->L4-->AL-->L5-->AL-->L6-->DM-->L7-->DM-->L8-->RW-->L9 L1-->IF-->L2-->DE-->L3-->RR-->STALL---->STALL---->STALL---->L4-->AL-->L5-->AL-->L6-->DM-->L7-->DM-->L8-->RW-->L9 </code></pre> For case 4, the value stored in memory by the second instruction is (presumably) not needed until the first Data Memory stage and the address generation part of the second instruction has no dependency on the first instruction. (L8 of the first instruction lines up with L6 of the second.) <pre><code> L1-->IF-->L2-->DE-->L3-->RR-->L4-->AL-->L5-->AL-->L6-->DM-->L7-->DM-->L8-->RW-->L9 L1-->IF-->L2-->DE-->L3-->RR-->L4-->AL-->L5-->AL-->STALL---->L6-->DM-->L7-->DM-->L8-->RW-->L9 </code></pre> (Since the writing to memory is a commitment of architectural state similar to writing the register, it might be more typical for a pipeline not to require the stored value until the RW stage.) Without bypassing all register source operands are retrieved from the register file in the Register Read stage. Since a new value is written to the register file in the Register Write stage, without bypassing the given 8-stage pipeline will require 5 cycles of stall for such dependent cases. <pre><code> L1-->IF-->L2-->DE-->L3-->RR-->L4-->AL-->L5-->AL-->L6-->DM-->L7-->DM-->L8-->RW-->L9 L1-->IF-->L2-->DE-->STALL---->STALL---->STALL---->STALL---->STALL---->L3-->RR-->L4-->AL-->L5-->AL-->L6-->DM-->L7-->DM-->L8-->RW-->L9 </code></pre> With bypassing, a dependent value can be communicated from the earliest stage it is available (the end of the second ALU stage for arithmetic instructions, the end of the second Data Memory stage for load instructions)--rather than the Register Write stage--to the earliest stage of the dependent instruction in which the value is needed (before the ALU stages for arithmetic instructions and address computation, before the Data Memory stages for stores if stores require the stored value early as seems to be the case in this pipeline)--rather than the Register Read stage. (Aside: Some pipelines perform the register write in the first half of the cycle and the register read in the second half of the cycle. Not only can this reduce the number of access ports needed for the register file, but it also allows values to be available from the register file one cycle earlier since the read of a newly written value can occur in the later half of the same cycle as the write. This reduces the amount of bypassing needed.)
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1. POpipeline stalling and bypassing examples
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1. USPaul A. Clayton
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1. USPaul A. Clayton
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