Databases
StackOverflow2013
Postsdbo
POCompiler bug, or misunderstanding of SystemVerilog? Undeclared port type works in simulation
 

Note that there are some explanatory texts on larger screens.

plurals
  1. POCompiler bug, or misunderstanding of SystemVerilog? Undeclared port type works in simulation
    primarykey
    data
    text
    <p>I have a module with a number of <code>input logic</code> and <code>output logic</code> ports, and one port that should be <code>input foo::bar</code>, where foo is a package, and bar is an enum. But, I left off the <code>input</code>, so it's just plain <code>foo::bar</code>. And yet, it still works in simulation (tests pass, and you can see on waveforms that the value is being transmitted correctly).</p> <p>From <a href="http://www.eda.org/sv/SystemVerilog_3.1a.pdf" rel="nofollow">the LRM</a>, we have:</p> <pre><code>inout_declaration ::= inout port_type list_of_port_identifiers input_declaration ::= input port_type list_of_port_identifiers | input data_type list_of_variable_identifiers output_declaration ::= output port_type list_of_port_identifiers | output data_type list_of_variable_port_identifiers interface_port_declaration ::= interface_identifier list_of_interface_identifiers | interface_identifier . modport_identifier list_of_interface_identifiers ref_declaration ::= ref data_type list_of_port_identifiers port_type ::= [ net_type_or_trireg ] [ signing ] { packed_dimension } </code></pre> <p>It's clearly not inout_dec, input_dec, output_dec, or ref_dec. Looking deeper at the LRM, <code>net_type_or_trireg</code> is <code>supply0 | supply1 | tri | triand | trior | tri0 | tri1 | wire | wand | wor</code> or <code>tri</code>, and it's not those.</p> <p>Could it be an interface_port_dec? Well, <code>interface_identifier ::= identifier</code> and <code>enum_identifier ::= identifier</code>. But, sure := isn't symmetric and transitive, so it's not true that <code>interface_identifier := enum_identifier</code>.</p> <p>What am I missing here?</p>
    singulars
    1. PO
      singulars
      1. PTAnswer
    1. This table or related slice is empty.
    1. PTQuestion
    1. USEML
    1. USdan
    plurals
    1. This table or related slice is empty.
    1. This table or related slice is empty.
    1. This table or related slice is empty.
    1. PO
      singulars
      1. PTAnswer
    1. VO
      singulars
      1. POCompiler bug, or misunderstanding of SystemVerilog? Undeclared port type works in simulation
      1. This table or related slice is empty.
      1. VTApproveEditSuggestion
    2. VO
      singulars
      1. POCompiler bug, or misunderstanding of SystemVerilog? Undeclared port type works in simulation
      1. This table or related slice is empty.
      1. VTUpMod
    3. VO
      singulars
      1. POCompiler bug, or misunderstanding of SystemVerilog? Undeclared port type works in simulation
      1. This table or related slice is empty.
      1. VTUpMod
    1. COIs this the simulator being more tolerant of syntax than the LRM allows?
      singulars
      1. POCompiler bug, or misunderstanding of SystemVerilog? Undeclared port type works in simulation
      1. USMorgan
 

Querying!

 
Guidance
A row detail

Detail views are divided into sections. All the information in the data section comes from columns in the selected row. The other sections display data from other, related rows.

Related data can be related in a to-one or a to-many fashion. Captions of data related in a to-many fashion link to a list view showing a filtered view of the table.

Try moving around until you find a non-empty to-many entry and click on the label to get to one. You can move back to the root by clicking on the database name in the header.

SQuiL has stopped working due to an internal error.

If you are curious you may find further information in the browser console, which is accessible through the devtools (F12).

Reload