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    <p>Check out <a href="https://standards.ieee.org/findstds/standard/1800-2012.html" rel="nofollow noreferrer">IEEE Std 1800-2012</a> &sect; 3.4 &amp; &sect; 24. For full description about <code>program</code> blocks.</p> <p>In a short, incomplete summary, a <code>program</code> block:</p> <ul> <li>cannot cannot contain <code>always</code> procedures, <code>primitive</code> instances, <code>module</code> instances, <code>interface</code> instances (<code>virtual interface</code> and port <code>interface</code> is allowed), or other <code>program</code> instances.</li> <li>specifies scheduling in the Reactive region. This prevents race conditions.</li> <li>has an extra system task <code>$exit</code>, which terminates the <code>program</code> instances that calls it. <ul> <li>The simulation will terminate when all <code>program</code> instances have exited.</li> </ul></li> <li>is mostly like a <code>module</code> block except as stated above.</li> </ul> <p>The idea of a <code>program</code> block is to create a clear separation between test and design. In earlier versions of SystemVerilog (pre IEEE 1800), instantiation of a <code>class</code> was often limited to <code>program</code> blocks. This emphasized the division of test and design. It also made <code>program</code> blocks vital for verification engineers that that wanted to use object orientated programming in their flow. Since IEEE 1800, a <code>class</code> can be defined and instantiated almost anywhere. As a result, <code>program</code> blocks became less sufficient. </p> <p>Today the opinion of usefulness of a <code>program</code> block is divided. From the last few conventions I been to, the trend seems to be in favor of abandoning <code>program</code> blocks. This is because the advantages can be achieved by other methods. Scheduling in the Reactive region can be done with <code>clocking</code> blocks. A <code>mailbox</code>, queue(<code>[$]</code>), or associative array (<code>[*]</code>) can be used for intelligently handling simulation terminate running multiple tests. Personally, I still like using <code>program</code> blocks and use <code>initial forever</code> as an <code>always</code> equivalent when needed. If you are planning to use UVM, then a non-<code>program</code> blocks test bench might work better for you.</p> <p>In the end, it really comes down to a methodology preference. It is best to evaluate and try it on your own.</p>
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    1. COThanks! I played around with program blocks, found that, while basic program blocks work, some features aren't supported by my simulator (compile-time error of "SystemVerilog construct not yet implemented"). Doesn't seem worth trying to figure out what features of program blocks work and what don't, since it sounds like I can get all of the benefits of program blocks using other means.
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