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    <p>If you want to do it this way, you'll have to write it as a static rule:</p> <pre><code>$(OBJDIR)/special_file.$(OE): special_file.c $(ECHO) "Compiling file $&lt; =&gt; $@" $(CC) $(CFLAGS) $(CFLAGS_SPECIAL) $(DEFINES) $(INCLUDE) $&lt; -o $@ </code></pre> <p>However, much simpler and more flexible is to use recursive variable naming. Do something like this:</p> <pre><code>special_file_FLAGS = $(CFLAGS_SPECIAL) $(OBJDIR)/%.$(OE): %.c $(ECHO) "Compiling file $&lt; =&gt; $@" $(CC) $(CFLAGS) $($*_FLAGS) $(DEFINES) $(INCLUDE) $&lt; -o $@ </code></pre> <p>The automatic variable <code>$*</code> expands to the stem (the part that matches <code>%</code>). Now when you build anything other than <code>special_file.c</code>, say <code>other_file.c</code>, make will expand <code>$(other_file_FLAGS)</code> which is empty. When you build <code>special_file.c</code>, make will expand <code>$(special_file_FLAGS)</code>.</p> <p>BTW, you should (almost) <em>never</em> list a directory as a prerequisite of a target. Search for other answers to find out why not and the right way to ensure the target directory is created.</p> <p>ETA:</p> <p>Target-specific variables are definitely a cool feature. I tend to not use them, though. Why? Because I prefer to separate my <em>data</em> from my <em>rules</em>.</p> <p>If you use target-specific variables, you are mixing together the rule syntax (the target) with the data syntax (the variable assignment). Using the recursive variable name method, I keep the rule syntax and the data assignment separate. What if I decide I need to change my pattern rule so that the target name changes? With target-specific variables I have to go through all my files and change the target names. With recursive variable naming, I just change the pattern rule and it Just Works.</p> <p>In my build environments I typically have makefiles containing only data (variable assignments), plus an <code>include</code> of a common makefile that declares all my rules. Avoiding the need to leak target formatting syntax all over my general data-driven makefiles, escaping from my uber-magical common rule definitions, keeps me from doing much with target-specific variables.</p>
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    1. POmake, write a rule for single file
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    1. COThanks also for suggestions.
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