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    <p>Draw a picture of what you really want. </p> <p>In your code, you are creating a flip-flop that asynchronously resets with the reset signal. However, then you add an additional condition after clock and separately from it that also impacts the output cont. In effect, it also asynchronously resets your flip-flop when clk='1' and cont=Ratio. My bet this is not what you want. Generally a register has only one asynchronous reset and it is connected to the global reset line and not ever to logic (logic can glitch and effect a reset).</p> <p>In addition, although a much simpler similar asynchronous reset coding style is specified by 1076.6-2004 (VHDL RTL synthesis coding standard), it is not well supported yet. Which may be why @phineas saw his version of the code work and you did not. </p> <p>What are you trying to accomplish with clk_en? Do you intend that it is active only for a 1/2 clock cycle and never valid at a rising edge of Clk? </p> <p>If clk_en is ok being a clock wide, then try the following:</p> <pre><code>Counting1 : PROCESS (clk, reset) BEGIN IF reset='1' THEN cont &lt;= 0; clk_en &lt;= '0'; ELSIF RISING_EDGE(clk) THEN if cont/=Ratio then cont &lt;= cont + 1; clk_en &lt;= '0'; else cout &lt;= 0 ; clk_en &lt;= '1'; end if; END IF; </code></pre> <p>end process;</p> <p>If you really need clk_en as a half clock wide, then you have some work to do. After I throw away extra stuff, what you coded for clk_en would similar to:</p> <pre><code>ClkEnProc : PROCESS (clk) BEGIN IF clk='0' THEN clk_en &lt;= '0'; ELSIF RISING_EDGE(clk) THEN if cont=Ratio then clk_en &lt;= '1'; end if; END IF; </code></pre> <p>end process;</p> <p>I would be surprised if you find a synthesis tool that will support that. You may need to compose your clock enable using both a rising edge flip-flop and a falling edge one. Using the clk_en from counting1 process, try the following:</p> <pre><code>ClkEnNegProc : PROCESS (clk) BEGIN IF FALLING_EDGE(clk) THEN clk_en_neg &lt;= clk_en; END IF; end process; clk_en_half &lt;= clk_en and not clk_en_neg ; </code></pre>
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    1. USJim Lewis
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