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POPartial FPGA reconfiguration and performance
 

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    <p>These questions may sound very esoteric to most, but I'd really like to know more about this stuff.</p> <h2>1st</h2> <p>I'm wondering how long does it take for an FPGA to reconfigure itself, from the time its modelled circuit is powered down to the time a new one is in place and operational.</p> <p>I am aware that Place-&amp;-Route is a costly process, but that is because the P&amp;R tools must <em>decide where to put</em> the components and <em>how to route</em> them.</p> <p>Consider that P&amp;R analysis is done, and all that's left is actually reconfiguring the FPGA: is that a slow process by itself? Can it be done hundreds or thousands of times per second?</p> <p>There are several implications for such a possibility that I'm curious about. To name 2, it could allow us to serve an FPGA to multiple concurrent "clients" (the same way a GPU is capable of rendering stuff for multiple different programs), or provide for extremely fine-tuned circuits for long number-crunching processes of well-defined but numerous processing stages of highly asynchronous processing (think: complex Haskell programs).</p> <h2>2nd</h2> <p>Anothing thing I'd like to ask is whether an FPGA can be partially reconfigured in realtime, while the modelled circuit is powered and operational, as long as the parts being reconfigured are powered off, of course.</p> <p>Several interesting implications would arise from such a possibility as well, for example allowing for realtime reconfigurable buses, hardware emulation of neural networks, etc.</p> <p>Are such things being extensively researched right now? And how likely are they to be researched in the future?</p>
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    1. COLooks like partial FPGA reconfiguration is possible, yes. I should have researched more before asking (https://en.wikipedia.org/wiki/Partial_re-configuration). That's also a duplicate (http://stackoverflow.com/questions/4387921/how-are-fpgas-updated). However, the 1st question stands still.
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    2. COWhy on earth would you want to re-configure anything 100s of thousands of times? FPGA is not GPU, and you don't need to perform P&R before partial reconfiguration, how it works is that you prepare your IPs that you want to reconfigure, you create multiple version of it for different scenario, then load them into the FPGA whenever they are needed. It takes seconds, not micro-seconds to do so.
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    3. COMaybe these articles can be helpful: http://www12.informatik.uni-erlangen.de/publications/pub2010/OWTK10.pdf , http://www.eetimes.com/design/programmable-logic/4014808/How-to-take-advantage-of-partial-reconfiguration-in-FPGA-designs
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