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    <p>the problem is, that your enable signal is to long! set the enable signal only for one clock cycle!</p> <pre><code> ... clk_enable_0_5mhz&lt;='0'; -- clear enable by default if temp &gt;= x"31" then temp &lt;= (others =&gt; '0'); clk_enable_0_5mhz &lt;= '1';-- set enable only for one clock cycle end if; ... </code></pre> <p>you don't need to add the enable signal to your sensitivity list, as the process will run synchronous to your clock signal anyway (except if reset asynchronously).</p> <pre><code>process(clk_50mhz, rst) begin if(rst = '0') then ... elsif (clk_50mhz'event and clk_50mhz = '1') then if(clk_enable_0_5mhz = '1') then ... </code></pre> <p>here's the testbench I used</p> <pre><code>-- testbench library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity pattern_tb is end pattern_tb; architecture Behavior of pattern_tb is component clk0_5mhz_top port ( clk_50mhz : in std_logic; rst : in std_logic; din : IN std_logic; dout : OUT std_logic; clk_enable_0_5mhz : inout std_logic ); end component; signal clk_50mhz : std_logic; signal rst : std_logic; signal din : std_logic; signal dout : std_logic; signal clk_enable_0_5mhz : std_logic; constant pattern: std_logic_vector(7 downto 0):="00110001"; begin uut: clk0_5mhz_top port map( clk_50mhz =&gt; clk_50mhz, rst =&gt; rst, din =&gt; din, dout =&gt; dout, clk_enable_0_5mhz =&gt; clk_enable_0_5mhz ); gen_clk: process begin clk_50mhz&lt;='0'; wait for 10 ns; clk_50mhz&lt;='1'; wait for 10 ns; end process; gen_sigs: process begin rst&lt;='0'; din&lt;=pattern(7); wait for 10 us; rst&lt;='1'; wait for 10 us; for i in 7 downto 0 loop wait until falling_edge(clk_enable_0_5mhz); din&lt;=pattern(i); end loop; wait; end process; end Behavior; </code></pre>
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    1. COThanks baldyHDL, I tired to implement your suggestions but there is no output i.e. dout remained '0' all the time and there are no errors and warnings.
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    2. COactually it does work! I added the testbench I used to the answer above.
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    3. CObaldyHDL, I think I know why it is working with your testbench because the code that you have suggested produces clk_enable_0_5mhz signal with 1us time period and each bit in your testbench is 1us length where as I need clk_enable_0_5mhz time period of 2us since it should detect the pattern 00110001 in din which contains each bit of length 2us so that's why I am not able to get the dout. Do you know how to solve this problem?
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