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POUsing queues in recursive properties
 

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    <p>I have some data from a 1 bit serial port which comes in multiples of bytes of variant lengths as such:</p> <pre><code>byte expected_1 [$] = {8'hBA, 8'hDD, 8'hC0, 8'hDE}; byte expected_2 [$] = {8'h01, 8'h23, 8'h45, 8'h67, 8'h89, 8'hAB, 8'hCD, 8'hEF}; </code></pre> <p>At each positive clock edge, one bit is sent. I need to testbench hundereds of sequences ( maybe thousand in the future ) so I want to automate the process with assertions in system verilog. The new 2012 standard allows for queues to be passed to properties, but can the queues be sent though a recursive property? I received some error about hierarchical ref.</p> <p>This is what I have so far (with help from @Greg <a href="https://stackoverflow.com/questions/17037889/serial-testbenching-and-assertions-with-system-verilog">here</a>): </p> <pre><code>default clocking sck @(posedge sck); endclocking : sck sequence seq_serial(logic signal, logic [7:0] expected); // check each bit byte idx = 7; (signal == expected[idx], idx--)[*8]; endsequence : seq_serial property recurring_queue(bit en, logic data, byte data_e [$]) int queue_size = data_e.size; logic [7:0] expected = data_e.pop_front(); if(queue_size != 0) ( !en throughout (seq_serial(data, expected) ##1 recurring_queue(en, data, data_e)) ); endproperty : recurring_queue `define ez_assert(exp) assert property (recurring_queue(en, data, exp)) else $error("Bad Sequence @ time: %t. Info: %m", $time); </code></pre> <p>Calling the assertion in my testbench should be as easy as this:</p> <pre><code>A1 : `ez_assert(expected_1); </code></pre> <p>The error messages read: </p> <pre><code>1) passing hierarchical ref to be used in another hierarchical ref is not supported 2) Illegal SVA property in RHS of'##' expression 3) Local variable queue_size referenced in expression before getting initialized </code></pre> <p>I'm open to other ideas for asserting long variable-length serial sequences.</p>
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    1. COthese error messages would be easier to follow if added to the end of the question.
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    2. COSmall errors need to be cleaned up before getting to the real problem. Assignment to a whole queue needs a single quote before the curly bracket (e.g. `q[$]='{...};`). Multi-line macro needs a backslash ('\') at the end of each line except the final line. Are sure passing a queue to a property is supported by your simulator?
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    3. COI need to correct myself for the single quote for full queue assignment. Queues are apparently the exception as there are clear examples in [IEEE Std 1800-2012](http://standards.ieee.org/getieee/1800/download/1800-2012.pdf) section 7.10 Queues, but is allowed (10.10.3). Structure literals (5.10), array literals (5.10), unpacked arrays (7.4), dynamic arrays (7.5), and associative arrays(7.8) use `'{` for full assignments.
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