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    <p>The ARM <em>cache</em> on an IMX25 (ARM926) is 16K Code, 16K Data L1 with a 32byte length or eight instructions. With the DDR-SDRAM controller running at 133Mhz and a 16bit bus the transfer rate is about 300MB/s. A cache fill should only take about 100nS, not 9uS; this is about 100 times too long.</p> <p>However, you have four other issues with Linux.</p> <ol> <li>TLB misses and a page table walk.</li> <li>Data aborts.</li> <li>DMA masters stealing.</li> <li>FIQ interrupts.</li> </ol> <p>It is unlikely that the LCD master is stealing enough bandwidth, unless you have a huge display. Is your display larger than 1/4VGA? If not, this is only 10% of the memory bandwidth and this will pipeline with the processor. Do you have either Ethernet or USB active? These peripherals are higher data rate and could cause this type of contention with SDRAM.</p> <p>All of these issues maybe avoided by writing your toggler PC relative and copying it to the IRAM. See: <a href="https://git.kernel.org/cgit/linux/kernel/git/stable/linux-stable.git/tree/arch/arm/mach-imx/iram_alloc.c">iram_alloc.c</a>; this file should be portable to older versions of Linux. The XBAR switch allows fetches from SDRAM and IRAM simultaneously. The <em>IRAM</em> can still be a target of other <em>DMA</em> masters. If you are really pressed, move the code to the <em>ETB</em> buffers which no other master in the system can access.</p> <p>The <em>TLB miss</em> can actually be quite steep as it may need to run several <em>single beat</em> SDRAM cycles; still this should be under 1uS. You have not posted code, so it is possible that a variable and/or other is causing a <em>data fault</em> which is not maskable.</p> <p>If you have any drivers using the <em>FIQ</em>, they may still be running even though you have masked the normal <em>IRQ</em> interrupts. For instance, the <strong>ALSA</strong> driver for this system normally uses the <em>FIQ</em>.</p> <p>Both the <em>ETB</em> and the <em>IRAM</em> are 32-bit data paths and low wait state. Either one will probably give better response than the DDR-SDRAM.</p> <p>We have achieved sub micro-second response by using a <em>FIQ</em> and <em>IRAM</em> to toggle GPIOs on an IMX258 with another protocol using bit banging.</p>
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