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POstate transition falling edge
 

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    <p>I am revisiting VHDL after many years. I am trying to setup a basic state machine with a counter trigger at some overflow period. </p> <p>For some reason I am getting state transitions on the falling edge of the m_tick clock. There should only be a transition on the rising edge based on the m_tick &lt;= '1' in the state process? I must be overlooking something. </p> <p>I am testing in isim. I am sure I'm probably doing some not very smart. </p> <p>Thanks.</p> <pre><code>entity nes_ctl is generic( N: integer := 3; --17 bit overflow 131k ); port( clk : in std_logic; n_reset : in std_logic ); end nes_ctl; architecture Behavioral of nes_ctl is signal count_reg, count_next: unsigned(N-1 downto 0); --counter to produce tick signal m_tick: std_logic; --state variable type state_type is (s0,s1,s2,s3,s4,s5); signal state_reg, state_next: state_type; signal reset: std_logic; --inverted reset signal begin reset &lt;= not(n_reset); --invert the reset signal --syncronos logic process(clk) begin if(reset= '1') then count_reg &lt;= (others=&gt;'0'); state_reg &lt;= s0; elsif (clk'event and clk = '1') then count_reg &lt;= count_next; state_reg &lt;= state_next; end if; end process; count_next &lt;= count_reg +1; --increment counter, will overflow m_tick &lt;= '1' when count_reg = 0 else '0'; -- tick on every overflow --STATE MACHINE process(m_tick) begin if(m_tick &lt;= '1') then --only when m_tick goes high case state_reg is when s0 =&gt; state_next &lt;= s1; when s1 =&gt; state_next &lt;= s2; when s2 =&gt; state_next &lt;= s3; when s3 =&gt; state_next&lt;= s4; when s4 =&gt; state_next&lt;= s5; when s5 =&gt; state_next &lt;= s0; end case; else state_next &lt;= state_reg; --keep same state. no latches. end if; end process; end Behavioral; </code></pre>
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    1. COWhat does a relational operator `<=` do on std_logic? If you want to detect a rising edge, `if rising_edge(m_tick)` would be the obvious way
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      1. USBrian Drummond
    2. COGood point. should have been if (m_tick = '1').
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    3. COMy logic was that m_tick triggered the process, so there was an edge on m_tick. The if(m_tick = '1') is the check to see if it was the rising edge. What is the defacto standard for such as check? rising_edge(m_tick) like you sugges?
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