Note that there are some explanatory texts on larger screens.

plurals
  1. PO[verilog]Activating LED with Pmod_KYPD combination
    primarykey
    data
    text
    <p>I'm using a <a href="https://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,940&amp;Prod=PMODKYPD" rel="nofollow">Pmod_KYPD</a> connected to a <a href="http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS2" rel="nofollow">Digilent FPGA</a>.</p> <p>My purpose is to activate the first LED on the board after the combination '123' is entered in to the keypad.</p> <p>I've downloaded the <a href="https://www.digilentinc.com/Data/Products/PMOD-KPD/PmodKYPD_ISE_Demo.zip" rel="nofollow">demo code</a> of the keypad from Digilent which works fine and it basically displays whatever pressed on from the keypad on to the 7-segment display.</p> <p>The demo code is composed of two parts, which are decode and display. I've modified the display code(only the second 'always' statement is my addition) like the following with a statement machine:</p> <pre><code>`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////////////////////////////// // Company: Digilent Inc 2011 // Engineer: Michelle Yu // Josh Sackos // Create Date: 07/23/2012 // // Module Name: DisplayController // Project Name: PmodKYPD_Demo // Target Devices: Nexys3 // Tool versions: Xilinx ISE 14.1 // Description: This file defines a DisplayController that controls the seven segment display that works with // the output of the Decoder. // // Revision History: // Revision 0.01 - File Created (Michelle Yu) // Revision 0.02 - Converted from VHDL to Verilog (Josh Sackos) ////////////////////////////////////////////////////////////////////////////////////////////////////////// // ============================================================================================== // Define Module // ============================================================================================== module DisplayController( DispVal, anode, segOut, led, clk, reset ); input clk; input reset; // ============================================================================================== // Additional Declarations // ============================================================================================== output reg [7:0] led; reg [1:0] state; // ============================================================================================== // Port Declarations // ============================================================================================== input [3:0] DispVal; // Output from the Decoder output [3:0] anode; // Controls the display digits output [6:0] segOut; // Controls which digit to display // ============================================================================================== // Parameters, Regsiters, and Wires // ============================================================================================== // Output wires and registers wire [3:0] anode; reg [6:0] segOut; // ============================================================================================== // Implementation // ============================================================================================== // only display the rightmost digit assign anode = 4'b1110; //------------------------------ // Segment Decoder // Determines cathode pattern // to display digit on SSD //------------------------------ always @(DispVal) begin case (DispVal) 4'h0 : segOut &lt;= 7'b1000000; // 0 4'h1 : segOut &lt;= 7'b1111001; // 1 4'h2 : segOut &lt;= 7'b0100100; // 2 4'h3 : segOut &lt;= 7'b0110000; // 3 4'h4 : segOut &lt;= 7'b0011001; // 4 4'h5 : segOut &lt;= 7'b0010010; // 5 4'h6 : segOut &lt;= 7'b0000010; // 6 4'h7 : segOut &lt;= 7'b1111000; // 7 4'h8 : segOut &lt;= 7'b0000000; // 8 4'h9 : segOut &lt;= 7'b0010000; // 9 4'hA : segOut &lt;= 7'b0001000; // A 4'hB : segOut &lt;= 7'b0000011; // B 4'hC : segOut &lt;= 7'b1000110; // C 4'hD : segOut &lt;= 7'b0100001; // D 4'hE : segOut &lt;= 7'b0000110; // E 4'hF : segOut &lt;= 7'b0001110; // F default : segOut &lt;= 7'b0111111; endcase end always @(posedge clk) begin if(reset) begin led &lt;= 8'b11111111; state &lt;= 0; end else begin case (state) 2'b00: begin if(DispVal == 1) begin state &lt;= state + 1; end //led &lt;= 8'b10000000; end 2'b01: begin if(DispVal == 2) begin state &lt;= state + 1; end else state &lt;= 0; //led &lt;= 8'b00000010; end 2'b10: begin if(DispVal == 3) begin state &lt;= state + 1; end else state &lt;= 0; //led &lt;= 8'b00000100; end 2'b11: begin led &lt;= 8'b11111111; end default: led &lt;= 0; endcase end end endmodule </code></pre> <p>But my modification is not working unfortunately. If I enter '123' from the keypad, the LED simply doesn't get activated.</p> <p>What should I change in my modification?</p> <p>Thanks. :)</p>
    singulars
    1. This table or related slice is empty.
    plurals
    1. This table or related slice is empty.
    1. This table or related slice is empty.
    1. This table or related slice is empty.
    1. This table or related slice is empty.
    1. This table or related slice is empty.
 

Querying!

 
Guidance

SQuiL has stopped working due to an internal error.

If you are curious you may find further information in the browser console, which is accessible through the devtools (F12).

Reload