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    <p>Dive over to ARM.com and grab the <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0337i/DDI0337I_cortexm3_r2p1_trm.pdf" rel="nofollow">Cortex-M3 datasheet</a>. Section 3.3.1 on page 3-4 has the instruction timings. Fortunately they're quite straightforward on the Cortex-M3.</p> <p>We can see from those timings that in a perfect 'no wait state' system your professor's example takes 3 cycles:</p> <pre><code>ASR R1, R0, #31 ; 1 cycle ADD R0, R0, R1 ; 1 cycle EOR R0, R0, R1 ; 1 cycle ; total: 3 cycles </code></pre> <p>and your version takes two cycles:</p> <pre><code>ADD R1, R0, R0, ASR #31 ; 1 cycle EOR R0, R1, R0, ASR #31 ; 1 cycle ; total: 2 cycles </code></pre> <p>So yours is, theoretically, faster.</p> <p>You mention "The removal of one memory fetch", but is that true? How big are the respective routines? Since we're dealing with Thumb-2 we have a mix of 16-bit and 32-bit instructions available. Let's see how they assemble:</p> <p>Their version (adjusted for UAL syntax):</p> <pre><code> .syntax unified .text .thumb abs: asrs r1, r0, #31 adds r0, r0, r1 eors r0, r0, r1 </code></pre> <p>Assembles to:</p> <pre><code>00000000 17c1 asrs r1, r0, #31 00000002 1840 adds r0, r0, r1 00000004 4048 eors r0, r1 </code></pre> <p>That's 3x2 = 6 bytes.</p> <p>Your version (again, adjusted for UAL syntax):</p> <pre><code> .syntax unified .text .thumb abs: add.w r1, r0, r0, asr #31 eor.w r0, r1, r0, asr #31 </code></pre> <p>Assembles to:</p> <pre><code>00000000 eb0071e0 add.w r1, r0, r0, asr #31 00000004 ea8170e0 eor.w r0, r1, r0, asr #31 </code></pre> <p>That's 2x4 = 8 bytes.</p> <p>So instead of removing a memory fetch you've actually increased the size of the code.</p> <p>But does this affect performance? My advice would be to <strong>benchmark</strong>.</p>
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    1. COawesome! thanks!
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