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    <p>Intel support 3 kinds of addresses:</p> <p>logical address --(segment unit)---> linear address ---(paging unit)---> physical address</p> <p>as you know, all kernel and user code access data or text thought virtual address (logical address in CPU). The address is translated into linear address as the following graph:</p> <p><img src="https://i.stack.imgur.com/GCm96.png" alt="enter image description here"></p> <p>As linux implementation does not support the concept of linear addressing and the segments is only provided for permission control. Linux kernel configures each segment's offset value to zero. That is why you can't see the linear address in kernel and kernel directly use virtual address on paging units.</p> <p>After getting the linear address, the MMU paging unit reference CR3 register to get base of paing table to generate physical address.</p> <p><img src="https://i.stack.imgur.com/JYL2C.png" alt="enter image description here"></p> <p>The same with cpu cache, the paging unit also has a TLB cache per CPU core to speed up the address translation that performed on memory.</p> <p>Reference: <a href="https://www.google.com/url?sa=t&amp;rct=j&amp;q=&amp;esrc=s&amp;source=web&amp;cd=1&amp;ved=0CC8QFjAA&amp;url=http://download.intel.com/products/processor/manual/253668.pdf&amp;ei=wJyRUYT3J8qOlQXDioDQCA&amp;usg=AFQjCNFP1iEex4YiE1Wcf2tDuab5OV_plQ&amp;sig2=zY0t1bm-mt24BRz1pnYDiw&amp;bvm=bv.46471029,d.dGI&amp;cad=rja" rel="nofollow noreferrer">intel64 software developer's manual</a></p>
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