Databases
StackOverflow2013
Postsdbo
PO8 bit ALU for microprocessor
 

Note that there are some explanatory texts on larger screens.

plurals
  1. PO8 bit ALU for microprocessor
    primarykey
    data
    text
    <p>I have a project where i am supposed to develop a RISC microprocessor . this involves creating an ALU in behavioral model . however there seems to be problems/errors/warnings while simulating the design . most of the operations work properly except following : </p> <p>COMPARING THE 2 INPUTS : when numbers are equal , zero flag is not getting set . ( unequal numbers are working properly ) . </p> <p>Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).</p> <p>( this appears every 1 ps , presumably due to the wait statement in the process )</p> <p>I Wish to work with std_logic_vector, even though i read that they are very messy . </p> <p>also, there is a problem when i try to use comparing commands ( which update the flags but dont store the difference in the output register ) . How are if commands executed in VHDL ?? are they executed at the same time ?? or line by line ??</p> <h1>CODE BELOW :</h1> <pre><code> LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ALU IS PORT( INPUT1 , INPUT2: IN STD_LOGIC_VECTOR(7 DOWNTO 0 ) ; CARRYIN : IN STD_LOGIC ; ZERO,CARRYOUT : OUT STD_LOGIC ; OUTPUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0 ) ; CONTROL : IN STD_LOGIC_VECTOR(7 DOWNTO 0 ) ) ; END ALU ; ARCHITECTURE OPERATION OF ALU IS SIGNAL TMP : STD_LOGIC_VECTOR( 8 DOWNTO 0 ) ; BEGIN PROCESS BEGIN IF( CONTROL = "00110000" OR CONTROL(7 DOWNTO 3 ) = "00001" ) THEN TMP &lt;= CARRYIN &amp; ( INPUT1 AND INPUT2 ) ; ELSIF( CONTROL(7 DOWNTO 3 ) = "00010" ) THEN TMP &lt;= CARRYIN &amp; ( INPUT1 OR INPUT2 ) ; ELSIF( CONTROL(7 DOWNTO 3 ) = "00011" ) THEN TMP &lt;= CARRYIN &amp; ( INPUT1 XOR INPUT2 ) ; ELSIF( CONTROL(7 DOWNTO 3 ) = "00100" ) THEN TMP &lt;= CONV_STD_LOGIC_VECTOR( ( CONV_INTEGER(INPUT1)+1 ) , 9 ) ; ELSIF( CONTROL(7 DOWNTO 3 ) = "00101" ) THEN TMP &lt;= CONV_STD_LOGIC_VECTOR( ( CONV_INTEGER(INPUT1)-1 ) , 9 ) ; ELSIF( CONTROL = "10001100" ) THEN TMP &lt;= '0' &amp; (NOT INPUT1) ; ELSIF( CONTROL(7 DOWNTO 3 ) = "11000" OR CONTROL(7 DOWNTO 2 ) = "110010" OR CONTROL = "110-11--" ) THEN TMP &lt;= CONV_STD_LOGIC_VECTOR( ( CONV_INTEGER(INPUT1)+CONV_INTEGER(INPUT2) ) , 9 ) ; ELSIF( CONTROL(7 DOWNTO 3 ) = "11100" OR CONTROL(7 DOWNTO 2 ) = "111010" OR CONTROL = "111-11--" OR CONTROL(7 DOWNTO 3 ) = "00000" OR CONTROL = "00111000" ) THEN TMP &lt;= CONV_STD_LOGIC_VECTOR( ( CONV_INTEGER(INPUT1)-CONV_INTEGER(INPUT2) ) , 9 ) ; ELSIF( CONTROL(7 DOWNTO 3 ) = "11010" OR CONTROL(7 DOWNTO 2 ) = "110110" ) THEN TMP &lt;= CONV_STD_LOGIC_VECTOR( ( CONV_INTEGER(INPUT1)+CONV_INTEGER(INPUT2)+CONV_INTEGER(CARRYIN) ) , 9 ) ; ELSIF( CONTROL(7 DOWNTO 3 ) = "11110" OR CONTROL(7 DOWNTO 2 ) = "111110" ) THEN TMP &lt;= CONV_STD_LOGIC_VECTOR( ( CONV_INTEGER(INPUT1)-CONV_INTEGER(INPUT2)-CONV_INTEGER(CARRYIN) ) , 9 ) ; END IF ; IF ( TMP( 7 DOWNTO 0 ) = "00000000" ) THEN ZERO &lt;= '1' ; ELSE ZERO &lt;= '0' ; END IF ; IF( CONTROL(7 DOWNTO 3 ) = "00000" OR CONTROL = "00111000" ) THEN TMP( 7 DOWNTO 0 ) &lt;= INPUT1 ; END IF ; OUTPUT &lt;= TMP( 7 DOWNTO 0 ) ; CARRYOUT &lt;= TMP(8) ; WAIT FOR 1 PS; END PROCESS ; END OPERATION ; </code></pre> <h1>testbench code</h1> <pre><code>LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; ENTITY test_tb IS END test_tb; ARCHITECTURE behavior OF test_tb IS COMPONENT ALU PORT( INPUT1 , INPUT2: IN STD_LOGIC_VECTOR(7 DOWNTO 0 ) ; CARRYIN : IN STD_LOGIC ; ZERO,CARRYOUT : OUT STD_LOGIC ; OUTPUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0 ) ; CONTROL : IN STD_LOGIC_VECTOR(7 DOWNTO 0 ) ) ; END COMPONENT ; signal i1,i2,ctrl,opt : std_logic_vector(7 downto 0 ) := "00000000" ; signal cin,cout,zero : std_logic := '0'; BEGIN uut: alu PORT MAP ( i1,i2,cin,zero,cout,opt,ctrl ) ; stim_proc: process begin i1 &lt;= "10000000" ; i2 &lt;= "10000000" ; ctrl &lt;= "11011010" ; cin &lt;= '0' ; wait for 5 ps; ctrl &lt;= "00111000" ; wait for 5 ps ; wait; end process; END; </code></pre>
    singulars
    1. PO
      singulars
      1. PTAnswer
    1. This table or related slice is empty.
    1. PTQuestion
    1. USAbhinav Vishak
    1. USAbhinav Vishak
    plurals
    1. This table or related slice is empty.
    1. This table or related slice is empty.
    1. This table or related slice is empty.
    1. PO
      singulars
      1. PTAnswer
    2. PO
      singulars
      1. PTAnswer
    1. VO
      singulars
      1. PO8 bit ALU for microprocessor
      1. This table or related slice is empty.
      1. VTUpMod
    1. COI cannot reproduce your issue. I use a testbench providing all the inputs to the ALU. Check whether your input vectors are properly defined. if it still doesn't work, please add your testbench code to the question!
      singulars
      1. PO8 bit ALU for microprocessor
      1. USbaldyHDL
    2. COTMP seems like you are using it more like a variable than a signal. Id also suggest a sensitivity list for the process.
      singulars
      1. PO8 bit ALU for microprocessor
      1. USVoider
 

Querying!

 
Guidance
A row detail

Detail views are divided into sections. All the information in the data section comes from columns in the selected row. The other sections display data from other, related rows.

Related data can be related in a to-one or a to-many fashion. Captions of data related in a to-many fashion link to a list view showing a filtered view of the table.

Try moving around until you find a non-empty to-many entry and click on the label to get to one. You can move back to the root by clicking on the database name in the header.

SQuiL has stopped working due to an internal error.

If you are curious you may find further information in the browser console, which is accessible through the devtools (F12).

Reload