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    <p>Welcome to Prolog programming! It's very cool that you're coming at it from the hardware, almost as far from this as you can get.</p> <p>I think I see two problems.</p> <p>The first one is that your definition leaves out the defining characteristic of the AND gate, which is that when both inputs are 1 the output will be 1. Your translation into Prolog is a little odd-looking but certainly should take this into account. So I think in Prolog what you're trying to say is this:</p> <pre><code>signal(R, 0) :- gate(X), gate_type(X, and), terminal_type(R, X, out), terminal_type(R1, X, in), signal(R1, 0). </code></pre> <p>This isn't the whole story though. You'll need this too:</p> <pre><code>signal(R, 1) :- gate(X), gate_type(X, and), terminal_type(R, X, out), terminal_type(R1, X, in), terminal_type(R2, X, in), R1 \= R2, signal(R1, 1), signal(R2, 1). </code></pre> <p>This might be correct, but the second problem is that <code>signal(t7, 1)</code> is not an assertion, so it doesn't wind up in your fact database. It's just a bald structure, so it doesn't add anything to your query. The simplest solution would be to just add it to your database directly:</p> <pre><code>signal(t7, 1). signal(t8, 1). </code></pre> <p>Then do your query:</p> <pre><code>signal(t9, X). </code></pre> <p>Or, you could <code>assertz/1</code> it:</p> <pre><code>assertz(signal(t7, 1)), assertz(signal(t8, 1)), signal(t9, X). </code></pre> <p>But that's kind of sloppy, because <code>assert</code> is a side-effect that isn't undone on backtracking.</p> <p>In practice, most of the time you either make something part of the dynamic query by passing it along, or you make it part of the fact database. Mixing the two gets hard to reason about.</p> <p>If I were you, I would probably simplify things by reducing the number of different fact "types" to something more like this:</p> <pre><code>% gate(Name, Type, Input1, Input2, Output) gate(a1, and, t7, t8, t9). </code></pre> <p>Then you could really simplify the predicates by quite a bit:</p> <pre><code>signal(Out, 0) :- gate(_, and, R1, R2, Out), ( signal(R1, 0) ; signal(R2, 0)). signal(Out, 1) :- gate(_, and, R1, R2, Out), signal(R1, 1), signal(R2, 1). </code></pre>
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    1. POGuidance with writing Prolog rule
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    1. USDaniel Lyons
    1. USDaniel Lyons
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    1. COThis is great. You've given me a few things to ponder about. I am going to try this shortly and rest assured I'll have some more feedback :p . Thanks again!
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    2. COSure thing. :) Feel free to drop me an email (check my profile) if you have questions that aren't a good fit for the S.O. format.
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    3. COAppreciate it. Quick note: Is `/=` a valid operator? Compiler says "Operator expected". Should that be `\==`?
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