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POVerilog Signed Multiplication "loses" the Signed Bit
 

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  1. POVerilog Signed Multiplication "loses" the Signed Bit
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    <p>I am writing a code which uses a multiplier module which returns weird answers when one of the inputs is a negative number. I am guessing this has to do with how Verilog treats signed numbers and the module is not storing the result properly in the 'reg signed out' decleration. All my input/output/wire/reg declarations are signed, so I am not sure what I am missing and what else I need to do to tell Verilog to take care of this. Sorry for the beginner question! </p> <p>For example,</p> <p>When X[0] is 1610 and Theta1[1] is -123, the result I am getting from the multiplier module is: 6914897148530</p> <p>Here are the relevant parts of my code:</p> <pre><code>module mult(in1, in2, out, mult_start); // multiplication module input signed [32-1:0] in1, in2; input mult_start; output signed [64-1:0] out; reg signed [64-1:0] out; always @(in1 or in2 or mult_start) begin if (mult_start) begin out &lt;= (in1 * in2) &amp; {64{1'b1}}; end else out &lt;= out; end endmodule module child_one (clk, rst_b, sig_start, Input_X, Input_Theta1) // Internal Variables Memory reg signed [`REG_LENGTH-1:0] Theta1 [0:217-1]; reg signed [`REG_LENGTH-1:0] X [0:216-1]; wire signed [`OUT_LENGTH-1:0] prod_1 [0:217-1]; reg signed [`OUT_LENGTH-1:0] prod_sum; wire signed [`OUT_LENGTH-1:0] sig_result; mult mult_001 (X[0], Theta1[1], prod_1[1], mult_start); mult mult_002 (X[1], Theta1[2], prod_1[2], mult_start); mult mult_003 (X[2], Theta1[3], prod_1[3], mult_start); mult mult_004 (X[3], Theta1[4], prod_1[4], mult_start); always @(posedge clk or negedge rst_b) begin if (sig_start == 1) begin if (state == 4'b0000) begin state &lt;= 4'b0001; // initialize state variable to zero k &lt;= 0; result_done &lt;= 0; index &lt;= 0; end else if (state == 4'b0001) // Start Multiplication Operation begin k &lt;= result_done ? 0 : k + 1; result_done &lt;= result_done ? 1 : (k == 10); state &lt;= result_done ? 4'b0010 : 4'b0001; mult_start &lt;= result_done ? 1'b1 : 1'b0; //mult_start &lt;= 1'b1; //state &lt;= 4'b0010; end else if (state == 4'b0010) // Stop Multiplication Operation begin k &lt;= 0; result_done &lt;= 0; mult_start &lt;= 0; state &lt;= 4'b0011; end end end </code></pre> <p>endmodule</p> <p>Thanks,</p> <p>Faisal.</p>
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    1. USFaisal Rasool
    1. USFaisal Rasool
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    1. COI don't know Verilog at all and I don't know why this question is tagged VHDL, but I cannot see how assigning to Theta1[0] affects any of the multiplier modules at all.
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      1. POVerilog Signed Multiplication "loses" the Signed Bit
      1. USBrian Drummond
    2. COsorry about both those things. The Theta1[0] example was something I added at the end to show the problem I was having n I didn't paste it properly. As for the vhdl tag, that was cos I thought the problem I am having is a hardware language issue and someone who knew HDLs could let me know what I am missing with regards to signed, two's complement, sign extend, or something like that...
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      1. POVerilog Signed Multiplication "loses" the Signed Bit
      1. USFaisal Rasool
    3. COThat's OK. I hear enough odd things about Verilog that I decided to avoid it - including that it does unsigned arithmetic by default; and signed and unsigned multiplication are somewhat different processes. All I can suggest is to create a testbench for the multiplier module and work on it in isolation - simplify it to "out <= (in1 * in2)", add assert/report to see its internals, or additional output ports for intermediate signals, until you understand it and it does what you expect - then add back in any other functionality you need. In VHDL, numeric_std.signed would make this module easy.
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      1. POVerilog Signed Multiplication "loses" the Signed Bit
      1. USBrian Drummond
 

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