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POStruggling with waiting for transfer completion with VHDL
 

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  1. POStruggling with waiting for transfer completion with VHDL
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    <p>I'm needing to do continual SPI communication to read values from a dual channel ADC I have, and have written a kinda state-machine to do so. However, it doesn't seem to be getting into the state that reads the second channel and I can't figure out why. here's the VHDL...</p> <pre><code>SPI_read: process (mclk) --command bits: Start.Single.Ch.MSBF.... constant query_x: unsigned(ADC_datawidth-1 downto 0) := "11010000000000000"; -- Query ADC Ch0 ( inclinometer x-axis) constant query_y: unsigned(ADC_datawidth-1 downto 0) := "11110000000000000"; -- Query ADC Ch1 ( inclinometer y-axis) begin if rising_edge(mclk) then -- when SPI is not busy, change state and latch Rx data from last communication if (SPI_busy = '0') then case SPI_action is when SETUP =&gt; SPI_pol &lt;= '0'; -- Clk low when not active SPI_pha &lt;= 1; -- First edge is half an SCLK period after CS activated SPI_action &lt;= READ_X; when READ_X =&gt; SPI_Tx_buf &lt;= query_x; -- Load in command y_data &lt;= "00000" &amp; SPI_Rx_buf(11 downto 1); SPI_send &lt;= '1'; SPI_action &lt;= READ_Y; when READ_Y =&gt; SPI_Tx_buf &lt;= query_y; -- Load in command x_data &lt;= "00000" &amp; SPI_Rx_buf(11 downto 1); SPI_send &lt;= '1'; SPI_action &lt;= READ_X; end case; else SPI_send &lt;= '0'; -- Deassert send pin end if; end if; end process SPI_read; </code></pre> <p>The command is sent to the Tx buffer, and the value from the last received data is written to a signal which is output to some seven segment displays. A pulse from SPI_send is required to start the transfer, and when started, SPI_busy is set high until the transfer is completed.</p> <p>Right now it'll only send the query_x over SPI, and I can know this since I can see it on the scope. Interestingly, however, It's outputting the same value to both displays which leads me to think that it's still getting into it's READ_Y state, but not changing the Tx Data it's outputting.</p> <p>I've been staring at this code for hours now, and I can't figure it out. Sometimes a fresh pair of eyes makes life easier, so if you spot anything please let me know. Also, I'm very open to suggestions of better ways to deal with this, I'm just learning VHDL so I'm not even sure I'm doing things the right way mostly!</p>
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    1. USKureigu
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    1. COI do not see the code for the tx portion and the state declarations. One suggestion would be to stick to the basic one process state machine template. Simplest to make busyX and busyY states.
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    2. COalso when you are learning HDL simulation is your friend, it makes debugging issues like this very easy.
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    3. COSorry, should have said the SPI master is a component, which returns SPI_busy when it's transmitting/receiving. This is just one process from my top level design so didn't want to include too much that might have been irrelevant. SPI_action starts in 'SETUP' state and then doesn't return there once running. Not sure I understand what you mean by your last sentence though.
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