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    <p>Your entity looks reasonable, though better names or comments on CPOL,CPHA would be useful!</p> <p>Partial answers :</p> <p>1) You CAN use it in your design as a component, but as previously mentioned, direct entity instantiation is simpler and less verbose.</p> <p>2) No you can't directly output from deep in the hierarchy, and even if you could it would be a terrible idea! </p> <p>Are you familiar with "Design Patterns" from C++, Ada or Java programming? If so, think of your top level design as the "Facade" pattern. </p> <p>It's the only thing the external world needs to know about your design. And it will often be written as structural HDL, instantiating your other entities, and making interconnections between sub-units and connections to external ports.</p> <p>There are ways to reduce the pain of these interconnections, especially across multiple layers of hierarchy, but ultimately you must break out the SPI signals to individual pins on the top level design, so that they can be connected to the correct wires on the PCB!</p> <p>3) would it be possible to set up a function to just say "Send this data over SPI and then return what's received" ... not a function, no. </p> <p>But certainly you can introduce a hardware wrapper to provide the rest of your design with a simple view of a complex task. For example, (assuming "send_packet" is asserted to write a byte on SPI, and "busy" goes high until the write is complete) you can create an entity taking an array of bytes and a "start" signal as inputs. Its architecture contains a process to count the bytes, outputting each in turn to SPI and waiting while "busy", and it can signal to its "caller" when done.</p>
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    1. POHow to effectively utilize a VHDL module?
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    1. USBrian Drummond
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