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POHow to effectively utilize a VHDL module?
 

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  1. POHow to effectively utilize a VHDL module?
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    <p><strong>There's a few questions in here, so bear with me, and thanks for taking the time to read this...</strong></p> <p>I recently wrote an SPI master, and have fully simulated it to make sure it works as expected. From here I'd like to use it in another design where I've already got a 7 segment display component set up to take the value received from an ADC on the SPI bus, however I think I've confused myself with things at this point.</p> <p>I need to send a pulse with other parameters to the SPI master to initiate a transfer, and wait on a busy signal to be de-asserted before I can send anything else. <strong>I'm not really sure how best way to implement the SPI master within the new design.</strong> </p> <p><em>Would I use it in the design as a component? is there a better way?</em> </p> <p>If it has to be a component, <em>is there any way I can set it up to directly output from that component to pins rather than me having to map to new inputs/outputs in the top level design?</em></p> <p>For example, I have SCLK, MOSI, MISO, and CS; <em>Can I not just have them output directly rather than having to be mapped through the top level?</em> Seems like it'd simplify the top level and make it less clunky.</p> <p>Also, <em>would it be possible to set up a function to just say "Send this data over SPI and then return what's received"?</em> </p> <p>I'm still getting my head around how to put these things together so help/examples would be greatly appreciated. It seems like all the examples/tutorials available are based on things like using two half-adders, logic gates, etc. which only help to a point when they're so simple.</p> <p>edit: Entity of my SPI Master</p> <pre><code>entity SPI_master is generic(data_width: integer := 8; clock_select: integer := 0); port(SCLK: out std_logic; MOSI: out std_logic; MISO: in std_logic; CS: out std_logic; Mclk_in: in std_logic; RST: in std_logic; CPOL: in std_logic; CPHA: in integer; send_packet: in std_logic; busy: out std_logic; Tx_data: in std_logic_vector(data_width-1 downto 0); Rx_data: out std_logic_vector(data_width-1 downto 0)); end SPI_master; </code></pre>
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      1. POHow to effectively utilize a VHDL module?
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    1. COIt might be helpful to add the entity declaration (not the architecture) for your SPI master to the post.
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      1. POHow to effectively utilize a VHDL module?
      1. USBrian Drummond
    2. COGood point. Added.
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