Databases
StackOverflow2013
Postsdbo
PO
 

Note that there are some explanatory texts on larger screens.

plurals
  1. PO
    primarykey
    data
    text
    <p>EDIT : further explanation re: third comment at the bottom. Apologies for the length of this!</p> <p>VHDL has functions and procedures too, just like C. (OK, C calls its procedures "void functions"!) And, just like C, you can call them from sequential code using the same kinds of sequential code constructs (variables, loops, if statements, case-statements which have some similarities to C's switch), and so on.</p> <p>So far, all this is synthesisable; some other VHDL features are for simulation only (to let you test the synthesisable code). So in simulation you can - like C - open, read and write files, and use pointers (access types) to handle memory. I hope you can see why these parts of VHDL aren't synthesisable!)</p> <p>But what is different in VHDL is that you need a few extra lines to wrap this sequential code in a process. In C, that happens for you; a typical C program is just a single process (you have to resort to libraries or OS functionality like fork or pthreads if you want multiple processes)</p> <p>But VHDL can do so much more. You can very easily create multiple processes, interconnect them with signals, wrap them as re-usable components, use "for ... generate" to create multiple processes, and so on. Again, all synthesisable : this imposes some restrictions, for example the size of the hardware (number of processes) cannot be changed while the system is running!</p> <p>KEY: Understand the rules for signal assignment as opposed to variable assignment. Variables work very much as in C; signals do not! What they do instead is provide safe, synchronised, inter-process communication with no fuss. To see how, you need to understand "postponed assignment", delta cycles, wait statements, and how a process suspends itself and wakes up again.</p> <p>You seem to be asking two questions here: </p> <p>(1) - can I use functions as in C? Very much so; you can do better than C by wrapping useful types and related functions, procedures in a package and re-using the package in multiple designs. It's a little like a C++ reusable class with some stronger points, and some weaker.</p> <p>(2) can I avoid entities, architectures and components altogether in VHDL? You can avoid components (search for "VHDL direct entity instantiation") but at some point you will need entities and architectures.</p> <p>The least you can get away with is to write a single process that does your job, receiving inputs (clk, count) on signals and transmitting to the LEDs on other signals.</p> <p>Create an entity with all those signals as ports, and an architecture containing your process, connecting its signals up to the ports. This is easy - it's just boilerplate stuff. On an FPGA, you also need to define the mapping between these ports and the actual pins your LEDs are wired to. Synthesise it and you're done, right? .. not quite.</p> <p>Create another "testbench" entity with no external ports. This will contain your entity (directly instantiated), a bunch of signals connecting to its ports, and a new process which drives your entity's input ports and watches its output ports. (Best practice is to make the testbench self-checking, and assert when something bad comes out!) Usually "clk" comes from its own one-liner process, and clocks both testbench and entity.</p> <p>Now you can simulate the testbench and watch your design working (or not!) at any level of detail you want. When it works - synthesise.</p> <p>EDIT for more information: re: components, procedures, functions.</p> <p>Entities/components are the main tool (you can ignore components if you wish, I'll deal with entities later). </p> <p>Procedures and functions usually work together in a single process. If they are refactored into a package they can be re-used in other like-minded processes (e.g. operating on the same datatypes). A common abstraction is a datatype, plus all the functions and procedures operating on it, wrapped in a package - this somewhat resembles a C++ class. Functions also have uses in any declaration area, as initialisers (aka "factory" pattern in software terms)</p> <p>But the main tool is the entity. </p> <p>This is a level that is probably unfamiliar to an embedded C programmer, as C basically stops at the level of the process.</p> <p>If you have written a physical block like an SPI master, as a process, you will wrap that process up in an entity. This will communicate with the rest of the world via ports (which, inside the entity, behave like signals). It can be parameterised via generics (e.g. for memory size, if it is a memory). The entity can wrap several processes, other entities, and other logic that didn't fit neatly into the process (e.g. unclocked logic, where the process was clocked)</p> <p>To create a system, you will interconnect entities, in "structural HDL code" (useful search term!) - perhaps a whole hierarchy of them - in a top level entity. Which you will typically synthesise into an FPGA.</p> <p>To test the system via simulation, you will embed that top level entity (=FPGA) in another entity - the testbench - which has no external ports. Instead, the FPGA's ports connect to signals inside the testbench. These signals connect to ... some of them connect to other entities - perhaps models of memories or SPI slave peripherals, so you can simulate SPI transactions ... some of them are driven by a process in the testbench, which feeds your FPGA stimuli and checks its responses, detecting and reporting errors.</p> <p>Best practice involves a testbench for each entity you create - unit testing, in other words. An SPI master might connect to somebody else's SPI slave and a test process, to start SPI transactions and check for the correct responses. This way, you localise and correct problems at the entity level, instead of attempting to diagnose them from the top level testbench.</p> <p>A basic example is shown <a href="http://vhdlguru.blogspot.co.uk/2010/03/entity-instantiation-easy-way-of-port.html" rel="nofollow">here</a> : </p> <p>Note that he shows port mapping by both positional association and (later) named association - you can also use both forms for function arguments, as in Ada, but not C which only allows positional association.</p> <p>What "vhdlguru" doesn't say is that named association is MUCH to be preferred, as positional association is a rich source of confusion and bugs.</p> <p>Is this starting to help?</p>
    singulars
    1. This table or related slice is empty.
    1. PODeveloping multi-use VHDL modules
      singulars
      1. PTQuestion
    1. PTAnswer
    1. USBrian Drummond
    1. USBrian Drummond
    plurals
    1. This table or related slice is empty.
    1. This table or related slice is empty.
    1. PODeveloping multi-use VHDL modules
      singulars
      1. PTQuestion
    1. This table or related slice is empty.
    1. VO
      singulars
      1. PO
      1. This table or related slice is empty.
      1. VTUpMod
    2. VO
      singulars
      1. PO
      1. This table or related slice is empty.
      1. VTAcceptedByOriginator
    3. VO
      singulars
      1. PO
      1. This table or related slice is empty.
      1. VTUpMod
    1. COI think you've just re-iterated my problem here, and I already understand the inherent differences between an HDL and C. What you said in (2) is exactly what I read in basic tutorials, and I was never trying to avoid entities. What I really still need to know if how I turn these entities into general purpose modules (equivalent to C functions) so that I can, say for example, just send an updated value to be displayed on a 7-seg display array.
      singulars
      1. PO
      1. USKureigu
    2. COThey already are general purpose modules, just instantiate them whenever you want and connect up signals. Perhaps I don't understand the question.
      singulars
      1. PO
      1. USBrian Drummond
    3. COSorry, that might be my fault, I probably wasn't too clear. My problem comes with the instantiating modules I've developed. There's loads of examples on VHDL to do one task, but I can't find much in the way of reseources to explain how to link all these parts together into one larger application specific design. For example, I have written an SPI Master, but I don't know what the best way to incorporate it would be. There's seems to be the options of procedures, functions and components in VHDL, and I'm just confused by the whole situation to be honest.
      singulars
      1. PO
      1. USKureigu
 

Querying!

 
Guidance
A row detail

Detail views are divided into sections. All the information in the data section comes from columns in the selected row. The other sections display data from other, related rows.

Related data can be related in a to-one or a to-many fashion. Captions of data related in a to-many fashion link to a list view showing a filtered view of the table.

Try moving around until you find a non-empty to-many entry and click on the label to get to one. You can move back to the root by clicking on the database name in the header.

SQuiL has stopped working due to an internal error.

If you are curious you may find further information in the browser console, which is accessible through the devtools (F12).

Reload