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2012-11-16T13:53:41.963
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<p>There is probably a very large number of ways to solve this, but without changing your code, much, here is one (note, not fully tested).</p> <ul> <li>Give each state a count output that depends on the clock rate.</li> <li>Establish a counter register big enough to hold the largest count.</li> <li>Decrement the count on each clock, reload it when it's zero.</li> <li>The reload value comes from the new state.</li> <li>Switch states on the last count before zero.</li> </ul> <h2> </h2> <pre><code>library IEEE; use IEEE.STD_LOGIC_1164.ALL; ENTITY programa IS PORT ( interrup : in Std_Logic_Vector (7 downto 0); clk, rst: in Std_Logic; led : out Std_Logic_Vector (2 downto 0) ); END programa; ARCHITECTURE arch_programa OF programa IS type state is (zero, one, two, three, four, five, six); signal pr_state, nx_state : state; signal A : Std_Logic_Vector (3 downto 0); signal count,pr_count:integer; --NOTE: Synthisizing integers is very unpredictable, should use unsigned BEGIN assign_counts:process(pr_state) begin --no idea what states need what delay, this is just an example case pr_state is when zero | one | two => pr_count<=10; when four => pr_count<=20; when others => pr_count<=50; end case; end process; process(interrup, pr_state) begin case pr_state is when zero => led <= "100"; A(0) <= interrup(7); nx_state <= one; when one => led <= "100"; A(1) <= interrup(6); nx_state <= two; when two => led <= "100"; A(2) <= interrup(5); nx_state <= three; when three => led <= "100"; A(3) <= interrup(3); nx_state <= four; when four => led <= "100"; if(A = "1111") then nx_state <= five; else nx_state <= six; end if; when five => led <= "010"; nx_state <=zero; when six => led <= "001"; nx_state <=zero; end case; end process; process(rst,clk) begin if(rst='1') then pr_state <= zero; count<=pr_count; elsif (clk'event and clk = '1') then if count=0 then count<=pr_count; elsif count=1 then pr_state <= nx_state; count<=count-1; else count<=count-1; end if; end if; end process; end architecture; --Test bench library IEEE; use IEEE.STD_LOGIC_1164.all; entity bench is end bench; architecture bench of bench is component programa IS PORT ( interrup : in Std_Logic_Vector (7 downto 0); clk, rst: in Std_Logic; led : out Std_Logic_Vector (2 downto 0)); END component; signal clk:std_logic:='1'; signal interrup:std_logic_vector (7 downto 0); signal rst:std_logic; constant freq:real:=1.0e6; begin do_reset:process begin rst<='1'; wait for 10 us; rst<='0'; wait; end process; clk<=not clk after 0.5 sec / freq; UUT:programa port map ( interrup => interrup, clk => clk, rst => rst); end architecture; </code></pre>
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1. POHolding an action in VHDL
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1. USJason Morgan
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1. COSynthesis of integers works just fine. But subtype them or at least set a range to control the size of the result! e.g. signal count : integer range 0 to 99;
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  USBrian Drummond

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