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POThread synchronization: How to guarantee visibility of writes
 

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    <p>There is already a lot of information on software and hardware memory models, memory fences, store/load reordering etc. However, it all seems to focus on guaranteeing the relative ordering of reads and writes to and from shared memory.</p> <p>Would it be legal behavior for such a system to delay the writes of a thread altogether for a potentially long time?</p> <p>For example, consider a thread that does some updates to a data structure in memory and then raises a flag that is supposed to notify other threads of the update:</p> <pre><code>(dataWritten is initially false) store value1 store value2 store value3 mfence store dataWritten (true) </code></pre> <p>According to most memory models I've read about, the memory barrier guarantees that any other thread cannot observe dataWritten as true, while still reading stale values 1, 2 or 3, i.e. it makes these writes atomic.</p> <p>But can I be sure that the writes will be seen <em>at all</em>? Would it be legal under the memory model to delay the writes indefinitely, as long as the flag isn't written sooner than the values?</p> <p>In database terms, can memory models be used to reason about durability (in addition to atomicity and consistency, which can be guaranteed by using memory fences and flags as in the example above)?</p> <p><strong>Update:</strong> <a href="https://stackoverflow.com/questions/11761552/guarantees-given-by-the-java-memory-model">Detailed semantics of volatile regarding timeliness of visibility</a> addresses the same topic in the context of the Java Memory Model, and <a href="https://stackoverflow.com/questions/7461484/memory-model-ordering-and-visibility">Memory model ordering and visibility?</a> for C++11. Does that discussion apply to hardware memory models as well, i.e. do CPU ISAs only give hard guarantees for correct visibility sequence, but "soft" guarantees for delayed visibility?</p>
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