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    <p>It's a bit hard to give specific advice, when not knowing the specifics of the device you are trying to interface to.</p> <p>However, a couple of general comments regarding your code:</p> <ul> <li><p>Your asynchronous process (the <code>PROCESS (CURR_STATE, INTR)</code>) will generate quite a few latches when synthesizing it, since you are not setting all your signals in all cases. <code>WR</code> and <code>READ_DATA</code> are for instance not being set in your <code>WAIT10</code> state. This will most probably lead to severe timing issues, so correcting this is something you'd absolutely want to do.</p></li> <li><p>The <code>WAIT10</code> state in the same process will give you a combinatorial loop, as it runs whenever <code>COUNTER_WAIT</code> is updated. As that state also updates <code>COUNTER_WAIT</code>, it will in theory just keep running, but in practice most synthesizers will just give you an error (I think). You'll need to move the incrementing to a synchronous/clocked process instead, which will also give you control over how long each cycle takes.</p></li> <li><p>Your 5 Hz processes seem to run on a separate clock (<code>CLK_5HZ</code>). I presume that the rest of your system is running at a faster clock? This essentially gives you two (or more) clock domains, that will need special interface logic for interfacing them with each other. A much, much better solution is to run everything on the same (fast) clock, and control slower processes using clock enables. Everything is thus inherently synchronized, and shouldn't give you any nasty timing surprises.</p></li> </ul>
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