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    <p>This piece of code should illustrate the difference b/w signals and variables. I inserted the processes directly into the testbench, so the code can be directly simulated with a HDL simulator of your choice.<br> After 10 ns the <code>start</code> event is fired and both processes are evaluated.<br> You should then see the expected result, namely <code>sig_out</code>going high after another 20 ns, whereas <code>var_out</code> should be high after only 10 ns.</p> <pre><code>library ieee; use ieee.std_logic_1164.all; entity sigvartest is end entity sigvartest; architecture behav of sigvartest is signal start : std_logic := '0'; -- event to start simulation signal x_sig : std_logic := '0'; -- signal tested in SIGPROCESS signal sig_out : std_logic := '0'; -- output of SIGPROCESS signal var_out : std_logic := '0'; -- output of VARPROCESS begin start &lt;= '0', '1' after 10 ns; -- pretty self-explanatory, start goes high after 10 ns SIGPROCESS: process(start) is begin if(rising_edge(start)) then x_sig &lt;= '1'; -- signal is scheduled to be assigned its new value, no immediate change! if(x_sig = '1') then sig_out &lt;= '1' after 10 ns; else sig_out &lt;= '1' after 20 ns; -- this part will execute end if; end if; end process; VARPROCESS: process(start) is variable x_var : std_logic := '0'; begin if(rising_edge(start)) then x_var := '1'; -- variable is assigned immediately if(x_var = '1') then var_out &lt;= '1' after 10 ns; -- this part will execute else var_out &lt;= '1' after 20 ns; end if; end if; end process; end architecture; </code></pre>
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    1. POSignals and Variables in VHDL
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    1. CO:Thank you very much for your help,but i don't use TestBenchm i used waveform in quartus to see the difference but it wasn't clear; can i see the difference using waveform simulation??
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